ARM announces 2GHz netbook CPU

By: Martin Høyer Kristiansen (test.delete@this.example.com), September 17, 2009 1:15 am
Room: Moderated Discussions
Jouni Osmala (josmala@cc.hut.fi) on 9/16/09 wrote:
---------------------------

>Millions of extra active transistors or hundreds of thousands of extra transistors
>are going to consume power, if everything else was kept the same.

A ROB is hardly millions of transistors. It's a very dense SRAM structure with busses and comparators.


>Secondly the thread was all about length of pipeline between fetch&execute times
>the clock speed. Aka thing called time it takes from instruction fetch to execute,

Which is only relevant on mispredicted branches. That is, it is *completely* irrelevant for 90% of executing code.

And while those extra stages that implement the renaming apparatus costs extra when a branch is mispredicted they greatly boost performance when branches are correctly predicted.

What is important is the schedule(dispatch)-execute latency.

By the way: It's pretty normal for high performance in-order cpus to use delay (or skewed) execution of simple instructions. With these instructions delayed a couple of cycle relative to loads a perceived one cycle load-to-use latency can be obtaind, but at the cost of increasing the mispredict latency!!!

>Your example lacks reasonable comparison to arm design within same process node.

Which you will never see. With ever shrinking feature size comes every higher relative signalling latencies.

It makes no sense to build a highly clocked wide superscalar in-order processor in 40nm because the thing would stall all the time.


>The thing isn't that OoO is highpower period. The thing is that OoO is higher power
>than inorder design with most equivalence.

For trivial levels of performance, yes. For anything high performance, not really (where are the high performance, low power in-order CPUs?).

And no. You cannot compare x86 & ARM
>and say they are most equivalent, since arm is the thing you use in sub 0.1W designs,
>and all the way designed for low power consumption. And x86 is the thing with most
>complex instruction decoders in the market today ;)

Decoders that take up a whopping 4% of an Athlon core (probably less for Phenom I/II).

Arm and x86 are actually quite similar in that they both have fewer registers than their peers, and therefore has a increased amount of false dependencies vis a vis other RISCs, hurting in-order implementations.

Cheers
Martin
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