ARM announces 2GHz netbook CPU

By: Wilco (Wilco.Dijkstra.delete@this.ntlworld.com), September 18, 2009 1:15 pm
Room: Moderated Discussions
Michael S (already5chosen@yahoo.com) on 9/18/09 wrote:
---------------------------
>Wilco (Wilco.Dijkstra@ntlworld.com) on 9/18/09 wrote:
>---------------------------
>>Cortex-A8 and Atom are similar 2-way in-order cores to compare with. You're not
>>going to get a better comparison than this. Cortex-A8 is pretty much the same as
>>Cortex-A9, with the key difference that it is in-order. In fact they are so similar
>>that you could argue that ARM should have skipped the A8 and immediately go OoO.
>>
>
>I don't agree that Cortex-A9 is equalt of Silverhorne when it comes to execution resuorces:
>1. Silverthorne is sort-of 2.5-way core in 2-way closes. With right input stream
>it could sustain load+two ALU operations.

Didn't we go over this before? ARM has SHIFT+ALU, MUL+ADD, LDM, conditional execution, base writeback etc. On average you need more x86 instructions than ARM instructions (when using the same compiler), so each ARM instruction is more powerful. However x64 is much closer due to the additional registers.

Consider an 4-word load multiple instruction with base update. While it takes 2 cycles to execute (integer L1 transfers 64 bits per cycle), you can execute 3 independent non-memory instructions underneath.

>2. Cortex-A9 claims "double the performance of previous ARM FPU", which probably
>means peak scalar double-precision throughput between 1/3 to 1/2 of Silverthorne.

There is no official spec apart from "at least twice as fast as A8", so AFAICT, single precision performance is 16 GFLOPS (quad FMAC) and double precision is 3GFLOPS at 2GHz. What's the peak for Silverthorne?

>Of course, on real-world compiled codes Cortex-A9 would be MUCH closer to his peak
>DFLOPs peak than Silverthorne would be to his, but that's another story.
>3. Another issue is L2 cache. It seems, Silverthorne's is much higher performance
>than Cortex-A9, esp. when it comes to latency. For bigger applications that could
>be a single most significant difference between the two, giving to inferior in most
>other aspects Silverthorne core a significant edge.

L2 latency on Cortex-A8 is 9 cycles. No L2 latency figures are published for A9 - the latency depends on the L2 size and actual frequency. This is an interesting feature, why stall longer than absolutely necessary when running at less than the maximum frequency?

Atom has 18 cycle latency (http://www.anandtech.com/systems/showdoc.aspx?i=3321&p=7), which is much higher than other low-end x86 processors.

>As to Cortex-A8, wasn't it just rushed out to the market half-baked? I can't believe
>that it is the based possible general-purpose-performance-oriented 2-way in-order ARM-Cortex+Neon design.

It was late and rushed indeed, and the 65nm OMAP3 chips don't look good on performance or power consumption.

>So what does Cortex-A9 use in order to keep level of illusion of serial execution required for compliance with ARM ISA?
>The A9 whitepaper insists on "Out of order write back of instructions" but without some additional hardware mechanism for rolling back speculative commits that alone wouldn't be compliant with ARM exceptions model.

There are several possible mechanisms for this, such as saving checkpoints for instructions that can trap, a data-less ROB (as mentioned in another message), etc. I don't know what the A9 does, ARM is keeping the details pretty secret.

Wilco
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