ARM announces 2GHz netbook CPU

By: Michael S (already5chosen.delete@this.yahoo.com), September 20, 2009 3:12 pm
Room: Moderated Discussions
Linus Torvalds (torvalds@linux-foundation.org) on 9/20/09 wrote:
---------------------------
>Michael S (already5chosen@yahoo.com) on 9/20/09 wrote:
>>
>>Seem like you quickly forgot the lesson of lmbench
>>producing total crap on Northwood P4 L2 latency
>>measurements.
>
>lmbench does fine on a lot of architectures. The numbers
>have been pretty darn reliable. The fact that prefetching
>and other issues can confuse it is irrelevant.
>
>In this case, I actually looked at the low-level latency
>output and varied the strides and test sizes by hand,
>just to verify the numbers. Will I guarantee that they are
>correct? No. But they are likely to be accurate.
>
>>How about running test of your own on Atom?
>
>How about you run the tests. You are the one that
>are making claims that aren't backed up by anything at all.
>
>I ran tests. Anandtech ran tests. The results are in the
>same ballpark. I know what I'm doing, and so generally does
>anandtech. If you want to show anything else, it's up to
>you. I'm not going to waste my time trying to prove your
>point, especially since I don't have any reason to believe
>in it.
>
>As I pointed out, the claims you quoted from the Intel
>whitepapers have absolutely zero to do with the only L2
>latency that matters - load-to-use. And your 9 cycle quote
>simply never talked about load-to-use.
>
>It's entirely possible that from a pure L2 array perspective
>the latency is 9 cycles. But it seems like it's taking quite
>a few more cycles to get the access started, and the total
>actual user latency is much higher.
>
>>Or, at least, run lmbench3 on Cortex-A8 (according to my
>>understanding, even you don't have yet Cortex-A9 based
>>general-purpose machine).
>
>I don't have an A8 either, and am not very interested in
>one. ARM gets interesting (outside of cellphones etc) only
>with Cortex-A9. If I think Atom is anemic, why would I ever
>be interested in an A8?
>
>And I repeat - I'm not the one claiming unbelievable numbers
>and disagreeing with other peoples published test-results.
>You are the one who should back up your numbers, not
>me.
>
>>>It also seems to have a memory parallelism of 1 (using the
>>>same benchmark), which makes it even sadder. So you have
>>>a slow L2, accessed by a in-order blocking core. The end
>>>result is not pretty.
>>
>>If L1D is indeed blocking then I agree.
>
>The L1D is almost certainly not blocking - in fact lmbench
>'par_mem' claims to get a parallelism of 3 on the L1 itself.
>But once you miss in the L1, it looks like the pipeline is
>halted, and in an in-order machine that means that you won't
>be getting any more parallelism.
>
>So 'par_mem' says memory parallelism goes down to roughly 1
>once you don't fit in the L1 any more.
>
>Again, if you can show otherwise, feel free to do so. But
>you'd better have something to back those numbers up with,
>rather than just argue on no merits what-so-ever.

You are right.
It's up to me to bring the numbers.
Unfortunately, right now I have no time at work and no Atom at home. It's not your problem, I know :(

>
>I'm sure you can get more memory parallelism using HT and
>prefetching, and you can claim that the benchmark is broken.
>Fine, but it gives believable results on other platforms,
>and they are 'believable' on atom too, since it's pretty
>much what you'd expect from an in-order design that has
>also been tweaked to be low-power (ie the core likely does
>not try to speculatively do L2 lookups in parallel with an
>L1 miss, so the load-to-use penalty of an L2 hit is quite
>likely to contain the cost of the L1 miss and possibly even
>a pipeline restart, whatever).
>
>>But I somehow don't believe that their benchmarks are
>>good enough to figure it out.
>
>.. and I don't believe you have shown anything better.
>
>I have numbers. You don't. I have used the chip. You
>apparently have not. Why are you even arguing?
>
>>>It's very much a "plodding" microarchitecture, I have yet
>>>to find a single area where it made me go "whee, that's
>>>very cool".
>>
>>So, even single-precision SIMD is not inspiring?
>
>Why would anybody care about floating point to begin with?
>
>That machine is not ever going to do anything where SD
>SIMD will ever matter. Games? Don't make me laugh. Same
>goes for photoshop filters. Video decoding? You need to
>do it on the graphics chip anyway.
>
>Not a single load I have would ever show any stunning SIMD
>performance.
>
>So no. I can't say that I've been inspired by some SIMD
>performance. Maybe others have seem Atom in a better light.
>I kind of doubt it.
>
>Linus
>

Well, our situation is different.
It's possible that pretty soon we're going to examine this board:
http://emea.kontron.com/products/boards+and+mezzanines/3u+compactpci/x86+processor/cp305.html
instead of this one that we currently use and don't like (not because of CPU but because of the chipset):
http://emea.kontron.com/products/boards+and+mezzanines/3u+compactpci/x86+processor/cp306.html

The application that will run on it does single-precision SIMD and pretty much nothing else.
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