anonymous (no@spam.com) on 9/20/09 wrote:
---------------------------
>>It's entirely possible that from a pure L2 array perspective
>>the latency is 9 cycles. But it seems like it's taking quite
>>a few more cycles to get the access started, and the total
>>actual user latency is much higher.
>
>Take a look at an Atom pipeline diagram, e.g. [1].
>
>In the best case you should be seeing 16 clocks total.
>
>AGU+DC1+DC2+EX1 = 4 clocks (initial L1d miss)
>L2 hit pipeline = 9 clocks (as per ISSCC 2008)
>SC+IS+IRF+AGU = 4 clocks (hidden because L2 can signal a hit early)
>DC1+DC2+EX1 = 3 (L1d hit this time)
>
>[1] http://tuvantinhoc1088.com/my_documents/my_pictures/Giainghia/Atom/pipeline.gif

Your calculation makes two assumptions:
1. L2 access is not initiated until after EX1 stage
2. There is no data bypass from L2 directly to the core.
It is possible that both assumptions are correct but it is not at all obvious from pipeline diagram.