ARM announces 2GHz netbook CPU

By: Linus Torvalds (torvalds.delete@this.linux-foundation.org), September 21, 2009 7:05 am
Room: Moderated Discussions
Wilco (Wilco.Dijkstra@ntlworld.com) on 9/21/09 wrote:
>
>What this doesn't explain is the measured 18 cycle number -
>although that could be the cost of TLB misses.

Well, my personal measurements that I quoted a few posts
earlier were in the 10.3-11.2ns range. So at the low end,
that does look like 16 cycles is likely (this was obviously
on a 1.6GHz Atom).

The numbers were fairly stable, and yeah, TLB overhead
might account for the rest. If I recall correctly (and
I used to know lmbench pretty well, but I didn't
re-check), lmbench just creates a singly linked list of
different sizes and times it, so yes, TLB overhead would
be visible.

That said, the areas measured are not that large, and the
TLB should cover the L2 cache easily (as long as the data
is reasonably dense and the stride isn't that large,
which it wasn't).

I suspect that the variation I saw may be due to simply
contention. I think the L2 is 8-way associative, and with
fairly random physical page allocation it's possible that
some of the runs (I tested different strides etc) simply
ended up having some contention on a few of the accesses.

So 16 cycles matches pretty well with the lowest numbers
I saw, and the higher numbers are "explainable".

Of course, it's still a very sad number. Core 2 has a ten-
cycle load-to-use L2 latency, but I'm sure it started the
L2 lookup speculatively in parallel with the L1 lookup,
and it probably had a more tweaked recovery too.

So I can understand why it happens. But 16 (or whatever the
exact number is) cycles is a long time, and what I really
hate is how it's all serialized. Two consecutive L2 misses
will apparently not go on in parallel even if they are
totally independent, so you'll see that whole long L2
latency quite a bit.

Linus
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