TOP3 blunders

By: ? (, September 30, 2009 1:26 am
Room: Moderated Discussions
Jouni Osmala ( on 9/30/09 wrote:
>>>Now you want to add a second order programmability over those millions of transistors
>>>already required to do the work of making first order programmability, by turning
>>>their special purpose function to a generic function.
>>> . . .
>>>The ancient method of providing ISA programmability to programmers was that they
>>>could turn couple of instruction to multiple instructions that would be issued over
>>>multiple cycles, but those instructions where normal instructions and nothing fancy.
>>>But JMP instruction +instruction cache does the same function but in a more generic
>>>way. And you don't need the extra costs in decoding phase with use of those.
>>So, IOW, with current ISA(s), providing a "second order programmability" is nothing
>>more than a bandwidth/latency problem?
>Actually that was my way of saying that ancient methods of rewriting ISA, doesn't
>really help. Since they are pretty much more restricted way of doing same thing
>as a normal function call. What was proposed in this board was something that (you
>couldn't really combine with OoOE and normal programming model )OR( would hamper
>instruction latencies so badly that it would be huge net loss).

Hmm, I agree with:

- that it would disrupt the normal programming model, mostly from the perspective of compilers. - OK, but this is what compiler research is for, including research in programming models.

- latencies of operations performed by generalized computing elements (CEs) would be different than latencies of more hard-wired units present in today's CPUs. If not latencies, then the frequency. - OK, but: they can be pipelined, there might be a lot more instances of a particular CE type, a more general CE can be *directly* used in more situations than a less general one.

- the amount of [transistors dedicated to routing packets/messages/data among CEs] is non-trivial. - OK, but: In worst cases scenarios, the routing itself would take multiple cycles. In best case scenarios, the routing itself could probably be implemented in such a way that it takes 1 cycle, or effectively no cycles at all (via pipelining). The *average* number of packets which would be routed per cycle depends on the probability of worst-case vs. best-base. If say ~95% of actual code falls in the best case, then you do not have a problem.

In addition, may I point out that in the suggested low-level programming model (for the sake of simplicity, you can think of it as TTA, or data-flow, or user-visible OoO engine) you/compiler are able to express that some low-level operations A, B and C should be executed in parallel. Whereas in today's x86 code you cannot express such a thing.

I agree, that the overall concept is more complex (in multiple non-trivial respects) compared to what can be found in today's x86 CPUs - but I think you (all) can agree with me that it is a legitimate alternative to what is happening today: spending the transistor budget on adding more cores and/or doing a more sophisticated code analysis at run-time in hardware. Imagine an alternative universe where the transistor budget is being spent in an alternative way ...
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TopicPosted ByDate
TOP3 blundersanon2009/09/25 06:38 PM
  TOP3 blundersrwessel2009/09/25 06:58 PM
  TOP3 blundersPotatoswatter2009/09/26 01:12 AM
    TOP3 blundersJouni Osmala2009/09/26 07:47 AM
    TOP3 blundersWilco2009/09/26 09:51 AM
      TOP3 blundersPotatoswatter2009/09/26 12:04 PM
        TOP3 blundersRagingDragon2009/09/28 01:58 PM
  TOP3 blunders?2009/09/26 02:44 AM
    TOP3 blundersanon2009/09/26 05:55 AM
      TOP3 blunders?2009/09/26 09:49 AM
        TOP3 blundersPotatoswatter2009/09/26 12:38 PM
        TOP3 blundersJouni Osmala2009/09/26 08:52 PM
          TOP3 blunders?2009/09/27 12:08 AM
            implementationAM2009/09/27 12:31 AM
          the generic mechanismAM2009/09/27 12:15 AM
            the generic mechanism?2009/09/27 01:30 AM
          TOP3 blunderssomeone2009/09/27 06:49 AM
            TOP3 blunders?2009/09/27 07:33 AM
              TOP3 blundersBlistering blue barnacles2009/09/28 07:44 PM
              TOP3 blundersslacker2009/09/29 06:28 AM
                (12nJ/cycle)*3GHz = 36W (NT)Michael S2009/09/29 07:31 AM
                  That's what I get for posting so early. (NT)slacker2009/09/29 05:17 PM
          TOP3 blunderskoby m.2009/09/29 06:26 AM
            TOP3 blundersJouni Osmala2009/09/29 10:05 PM
              TOP3 blunders?2009/09/30 01:26 AM
    TOP3 blundersPotatoswatter2009/09/26 06:11 AM
      TOP3 blunderssomeone2009/09/26 08:26 AM
    ISA extensions - tensilica?David Kanter2009/09/26 09:17 AM
      ISA extensions - StretchWes Felter2009/09/26 10:24 AM
        ISA extensions - Stretch?2009/09/26 12:14 PM
          ISA extensions - StretchGabriele Svelto2009/09/28 02:14 AM
  TOP3 blundersanonymous2009/09/26 05:23 AM
  TOP3 smart movesanonib2009/09/26 06:11 PM
    TOP3 smart movesDavid W. Hess2009/09/26 06:55 PM
      TOP3 smart movesRichard Cownie2009/09/27 12:57 PM
        TOP3 smart movesRagingDragon2009/09/28 02:46 PM
    TOP3 smart movesa reader2009/09/27 07:44 AM
    TOP3 smart movesRichard Cownie2009/09/27 11:12 AM
      TOP2 probably illegal smart movesRichard Cownie2009/09/27 12:43 PM
        TOP2 probably illegal smart movesnn2009/09/27 06:27 PM
        TOP2 probably illegal smart movesDavid Kanter2009/09/29 12:48 AM
          TOP2 probably illegal smart movesRichard Cownie2009/09/29 09:31 AM
            TOP2 probably illegal smart movesMichael S2009/09/29 10:04 AM
              TOP2 probably illegal smart movesDavid Kanter2009/09/29 12:35 PM
              TOP2 probably illegal smart movesRichard Cownie2009/09/29 03:28 PM
              TOP2 probably illegal smart movesJouni Osmala2009/09/29 10:08 PM
              Link to good analysis on the matter.Jouni Osmala2009/09/29 10:22 PM
                Link to good analysis on the matter.Richard Cownie2009/09/30 08:59 AM
  TOP3 blunder of todayMichael S2009/09/29 03:31 AM
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