Mat (m@t.com) on 10/1/09 wrote:
---------------------------
>>>>arm did come up with a few tricks to lower the power
>>>>consumption of oooe, e.g. use a checkpointing mechanism to
>>>>reduce the power required to keep track of which renamed
>>>>registered can be freed.
>>>>
>>>Where does it say that checkpointing is used in the A9?
>>
>>read the patents.
>
>Good point, doing a quick search on renaming yields interesting results, many have
>pipeline diagrams looking like the A9 whitepaper:
>
>http://v3.espacenet.com/searchResults?bookmarkedResults=true&submitted=true&DB=EPODOC&locale=en_gb&sf=a&FIRST=1&CY=gb&LG=en&&TI=&AB=renam*&PN=&AP=&PR=&PD=&PA=ARM&IN=&EC=&IC=&=&=&=&=&=

Interesting, the patents contain quite a lot of info. Some of the key details of the OOOE:

* 56 physical registers (32 architectural, 24 rename, ie. instruction window of up to 24 instructions or ~12 cycles, enough to hide a L1 miss)
* integer renaming only, VFP/Neon are in-order
* separate rename and restore table, allowing single cycle restore after exceptions, mispredicts or interrupts
* loads/stores/branches and conditionally executed instructions are speculated
* cache/TLB miss, ECC failure, data abort etc is checked after critical data is returned from the L1 cache, so load data may be invalid
* instructions are grouped with a previous speculated instruction. The rename mappings for each group are placed in a FIFO
* the restore table is updated with the rename mappings of the oldest group when its speculated instruction completes. This means the restore table contains the mapping of non speculated instructions (rolling back to this state gives the correct architectural state on an exception/mispredict etc). Any instructions in this group no longer need to be tracked and are considered completed (even if they haven't produced their result yet).
* the FIFO is also used to free unused rename registers as groups complete (this means that rename registers are often freed before the instruction computing the new value for the same architectural register completes)
* a register is reused if the register has been written, no reads are waiting to be issued, and it is no longer speculated or in the restore table
* instructions needing many rename registers (ldm/stm) get a small number of renames, and receive more rename registers while they execute to avoid blocking renaming of later instructions or using up most rename registers before actually needing them


>And noticing the inventors are French it seems that A9 was developed by the Sophia team of only 30 engineers. http://www.newelectronics.co.uk/article/11633/ARM-expands-Cortex-range.aspx
>>
>
>I find that quite astonishing given the complexity of building an OOOE machine. Even more curious then that simpler in order A8 was developed by 70 odd engineers - http://www2.electronicproducts.com/Product_of_the_Year_Story_Behind_the_Story_The_ARM_Cortex-A8_Processor_IP-article-sbsjh-arm-mar2006-html.aspx

It's even more impressive given that Cortex-A8 took longer.

>Any idea on the team size for Atom, can't believe it's the whole Austin centre?

Wilco