Mark Roulo (nothanks@xxx.com) on 9/29/09 wrote:
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>Linus Torvalds (torvalds@linux-foundation.org) on 9/29/09 wrote:
>---------------------------
>>And the thing is, in-order hits a huge complexity and
>>performance wall. I can't recall anybody ever having done
>>more than two-way superscalar, even on things that are
>>much easier to decode than x86. There's just not enough of
>>an upside to the complexity ....
>
>My recollection of SuperSPARC was that it was 3-issue and in-order.
>
>Wiki claims that UltraSPARC, which came later, was 4-issue
>and in-order.

Right you seem to be. And I have to admit that I should
have remembered the Alpha 21164, which was also quad-issue.

So it's been done, and it's generally much simpler to do
on fixed-width (and simple) instruction sets. I do think
that the upside tends to be fairly limited, and at least
on the 21164 you had to have a pretty specific instruction
mix (and I think the four instructions had to be 16-byte
aligned) to actually get quad-issue.

But clearly I was wrong. Dual-issue may be the common case,
but three and four have both been done.

>Neither of these were particularly noted for their
>performance, of course ...

The 21164 did very well, though. It was the performance
champ for a while. Of course, the PPro came out a bit
later, and shocked the RISC people with it's superior
integer performance (although I have this dim memory of
the better PPro numbers later turning out to be dubious).

So there have been very successful quad-issue in-order
cores.

Linus