3- and 4-issue in-order CPUs

By: Michael S (already5chosen.delete@this.yahoo.com), September 30, 2009 1:01 am
Room: Moderated Discussions
Mark Roulo (nothanks@xxx.com) on 9/29/09 wrote:
---------------------------
>Linus Torvalds (torvalds@linux-foundation.org) on 9/29/09 wrote:
>---------------------------
>>Mark Roulo (nothanks@xxx.com) on 9/29/09 wrote:
>>---------------------------
>>>Linus Torvalds (torvalds@linux-foundation.org) on 9/29/09 wrote:
>>>---------------------------
>>>>And the thing is, in-order hits a huge complexity and
>>>>performance wall. I can't recall anybody ever having done
>>>>more than two-way superscalar, even on things that are
>>>>much easier to decode than x86. There's just not enough of
>>>>an upside to the complexity ....
>>>
>>>My recollection of SuperSPARC was that it was 3-issue and in-order.
>>>
>>>Wiki claims that UltraSPARC, which came later, was 4-issue
>>>and in-order.
>>
>>Right you seem to be. And I have to admit that I should
>>have remembered the Alpha 21164, which was also quad-issue.
>>
>>So it's been done, and it's generally much simpler to do
>>on fixed-width (and simple) instruction sets. I do think
>>that the upside tends to be fairly limited, and at least
>>on the 21164 you had to have a pretty specific instruction
>>mix (and I think the four instructions had to be 16-byte
>>aligned) to actually get quad-issue.
>>
>>But clearly I was wrong. Dual-issue may be the common case,
>>but three and four have both been done.
>
>Yep. I suspect, however, that the 3rd and 4th pipes help very little
>for the SPARC, and I don't see how they could have helped the Alpha
>on integer loads as only two of the pipelines were for integer stuff.
>

UltraSPARC is pretty unusual in the balance (or lack of) between memory instructions and "other" integer instructions. I can't think about any other wide superscalar processor that can issue only one load or one store per clock. However, from theoretical point of view UltraSPARC is capable of issuing four integer instructions per clock: 2 to ALUs, 1 to LSU and 1 to branch unit.

Please, don't forget Power6 and Itanium2. Both are examples of working wide superscalar in-order engines.

Looking at integer resources only, Power6 has 2 FXUs, 2 LSUs and one branch unit for peak integer issue rate =5.

Itanium2 integer side is wider yet (6 pipes) and has fewer limitations on selection of instructions in the issue group. In fact, if you want all 6 instructions could be of integer ALU type.

Earlier example of wider-than-2-way in-order integer engine is IBM Power2 (2 FXU/LSU + 1 branch unit + 1 conditional registers unit).
AFAIR, MIPS R8000 also was capable of issuing more than 2 integer instructions per clock. 2 ALU + 2 AGU or something like that.
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