Hot Chips XXI Preview

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Hot Chips Preview

At the end of this month Hot Chips XXI will be held at Stanford University in Palo Alto. Hot Chips is a relatively unique conference, focused on microprocessors and related topics, with an emphasis on industry and a presence from academia. The program for Hot Chips XXI was put out in early June, and has quite a few promising papers. In this preview, we’ll try to collect some interesting questions and thoughts about the topics to be presented later this month.

Sunday Tutorials

Hot Chips kicks off with a morning tutorial covering the three major commodity system interconnects: HyperTransport 3, PCI-E gen 3 and QuickPath nee CSI. With an hour per talk, this should provide an interesting comparison that will undoubtedly reveal many techniques commonly used by all three camps (AMD, PCI-SIG, Intel) to achieve >6GT/s rates. Of particular interest to the author is the accuracy of our earlier report on CSI.

A four hour afternoon tutorial focuses on the OpenCL API for parallel computing. In many ways, OpenCL will be the catalyst for GPGPU adoption – existing proprietary approaches are simply are not palatable for the industry as a whole. Software developers are simply not interested in developing for a single vendor’s hardware. Of course, one interesting question will be the variety of hardware support – AMD, Intel and Nvidia are all obviously on-board, but how long will it be before embedded hardware vendors join in? Another key question is the extent to which OpenCL can readily generate efficient code for the various GPU architectures, although that also lies upon the shoulders of the hardware vendors to create a proper back-end.

Day 1

The first session focuses on servers, with presentations on AMD’s Magny Cours (which features two 6-core CPUs in a package), Intel’s Nehalem-EX and blade servers. Most of the architectural details for these two are known already; hopefully frequency, performance and power numbers will be forthcoming. Magny Cours will be the first demonstration of commodity multi-chip packages (MCP) for a processor with an integrated memory controller and on-die interconnects. The big question is how will performance/core scale compared to a 6-core device? History (particularly Intel’s earlier MCP designs) seems to suggest that it should drop due to frequency decreases, increased snoop bandwidth and other system level issues. That may not be an issue for Magny Cours, as unlike Intel’s earlier MCPs, they have sufficient memory bandwidth and processor interconnects.

The server session is followed up by a keynote from Jen-Hsun Huang; hopefully he’ll don more of an engineering perspective than usual in this address. Following that is an I/O oriented session with presentations on a USB3 storage controller, Luxtera’s silicon photonics and Intel’s I/O Hub for Nehalem.

Session 3 is solely focused on academia – a pleasant, forward looking interlude between industrial presentations. There will be three presentations on parallel programming research from Berkeley, UIUC and Stanford. Undoubtedly they will all emphasize the necessity and ability to harness multi-core processors (including GPUs). The Berkeley Lab is the oldest and has the most well documented (and aggressively marketed) approach, while Stanford’s lab was just recently funded and UIUC falls in between. The latter two have yet to really articulate their approach to the broad public.

The next and last session of the day focuses on three client processors and a chipset. It leads off with the first technical discussion of Intel’s Moorestown processor – hopefully with performance and power data and a detailed discussion of architectural improvements over the prior generation. The power and thermal envelop will be of substantial interest as it determines what markets Intel will be able to pursue. In addition to modest power under load, low idle power will be essential for battery operation and a reasonable (0.5-1W) TDP is needed for the smallest form factors. TI will present the OMAP4, a mobile phone oriented SOC (system on a chip) which features a dual-core Cortex A9 and should present an interesting contrast to Moorestown. In many respects, the OMAP4 is the best yardstick to measure Intel’s efforts against – as TI is an entrenched player in the mobile market and their products directly address those needs.

Nvidia will present their Ion chipset for Atom and perhaps discuss plans for working with future Moorestown based devices (or glossing over that roadmap difficulty). Last, Intel will discuss Westmere (and the new crypto instructions in SSE 4.2) and Nehalem in mainstream desktop and notebook products.

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