Well, this one isn’t really my own. It is *much* too good for that. This piece is instead from someone that frequently provides observations and opinions on the processor and memory market to myself and a few priviledged others. This one is particularly interesting and amusing, so I asked for permission to reproduce it here as an ‘anonymous’ contribution. I think you all will enjoy this piece.
I don’t buy any of those supermarket tabloids featuring alien abductions and such. Nor the movie star-oriented pubs with columns about which young lady just got a remarkably larger bustline overnight. That sort of gossip doesn’t appeal to me.
But tech gossip does appeal to me, which means I like to follow the Brit site “The Register”. Now, a goodly portion of their postings are pure fiction, which is normal for a gossip rag (or site). But sometimes the most obviously phony items turn out to be completely factual.
Ahem. I call your attention to the item today (the 16th) on Intel’s B1 Camino stepping. According to The Register, the chip fails when power is applied to it. Ridiculous! _Obviously_ phony gossip, right?
Uh, mebbe not?
Since I’m not working for a living, and since TV soap operas don’t appeal to me, and it’s hard finding good SF (non-fantasy variety) books these days, I have all the time I need to follow tech news via the net. My primary interest is in CPUs for desktop computers, a field that is gonna get interesting again real soon as K7 shipments start. My secondary interest is in computer memory, and the DRAM division has been _very_ interesting of late.
For instance, Micron is admittedly sitting on a growing inventory of unsold DRAMs. That’s a really stupid thing to do in a falling market. It’s _obviously_ a stupid thing to do. I expect Micron to do the obvious thing shortly, which means I expect to see DRAM pricing drop even lower shortly.
But the most interesting thing going on in the DRAM world (to gossip addicts like me) is Intel’s (and Rambus’s) Direct Rambus (DRDRAM) initiative, which as we all know was once going to take over all the computing world this summer. Some folk still think it’s gonna take over all the computing world, if not as quickly as was formerly believed.
Please allow me to astonish all of you by saying something good about DRDRAM. Every upcoming desktop CPU whose design has not yet been frozen, and some whose design _has_ been frozen, will include a direct DRAM interface. The path from the CPU to the DRAM will be chip-to-chip. No chipset intermediary. This is to reduce latency. And just about all of these upcoming CPUs will use the DRDRAM interface because of its low pin count. (Never mind that I’m beginning to think a low pin count is _all_ DRDRAM has going for it.)
However, it was this July – yes, next month – that DRDRAM was originally gonna take over the world. But then Intel produced samples of its i820 “Camino” chipset. To its horror, Intel discovered the i820 was disastrously slow. So much so that Intel immediately made the decision to postpone DRDRAM until September, when a newer version of the i820 could be made using smaller design rules. Intel assigned the internal code “B0” to the new, shrunken i820, which as The Register explains to us, means Intel anticipated that the new stepping would be a mass-production part.
Whoops! B0 didn’t work either, and Intel modified its estimated Camino production delivery to “the end of September” and immediately began work on the B1 stepping.
And today the gossip rag The Register reports that B1 fails when power is applied, which as we all know is a ridiculous assertion. The question is, is this ridiculous assertion true? I say, mebbe. I don’t say yes, mind you, but I can make a case for mebbe.
The problem Intel has been having with the various steppings of the i820 is not that the logic design is faulty. The problem has been that the part is too slow (a problem shared by the memory makers, the ones beginning to produce the DRDRAM memory chips). Remember, the B0 used reduced design rules and still proved to be too slow. So B1 undoubtedly uses yet-further reduced design rules, the smallest Intel can produce and still have hope of mass production late this year. [My guess is that B0 used .20u and B1 uses at least .18u and perhaps even .16u or so. This is a pure hunch on my part.]
Let’s talk about what the i820 is and what it does. The i820 is a chipset part. It sits between the CPU’s I/O ring (which operates at 3.3v) and the DRAMs and other stuff (that operate at 3.3v). Everybody knows what you have to do to get small silicon geometries to work: you have to lower the voltage applied to the small-geometry portion of the chip. That’s why my K6-2/400 uses a 3.3v supply for the I/O ring and a 2.2v supply for processor logic (which is most of the chip). That’s at .25u, mind you.
I don’t know what the design rules are in the 3.3v I/O ring portion of my K6-2/400, but it would’t surprise me if .4u was used, or maybe even bigger than that. Hey, the I/O ring only has to run at 100MHz!
Now let’s think about what the i820 does. It has to send and receive data to and from the DRDRAM RIMMs at an 800MHz rate. Not 100MHz. 800MHz. The i820 designers do not have the luxury of using a big slow I/O ring. They do _not_! And remember, the i820 is also supposed to have a 4X AGP port.
Because of the high-speed I/O requirements (800 MHz), Intel’s designers were probably forced (given the slowness of earlier i820s using larger design rules) to use unusually small design rules (if not as small as .18u or .16u) in the i820’s I/O ring.
What happens if you sandwich a chip using too-small geometries between two 3.3v chips? It’ll fail when the power is turned on, that’s what.
Now, what is today’s absurd, ridiculous rumor on The Register? Why, that the new B1 stepping of the i820 Camino fails when power is applied.
The fallback for memory chips and i820 chipsets that won’t run at 800MHz is to run them more slowly. Today’s news (_not_ on The Register) from Samsung is that its customers have zero interest in 600MHz DRDRAM.
And now you should understand why it is almost absolutely certain that Intel will imminently announce a new high-end chipset that supports PC133 DIMMs.
I hope the folk who’re designing DRDRAM interfaces into their new CPU chips have a Plan B.
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