A DRAMing Failure
When Intel decided to abandon DRDRAM and support DDR for mainstream use, DDR unquestionably became the dominant memory type. However, many of Intel’s early technical reservations about DDR proved to be quite valid. No registered DDR-400 DIMMs are available for servers, and two different specifications emerged for DDR-400 on the desktop; one for Intel chipsets and one for everything else. Moreover, it became clear with the release of the 533 and 800MHz front side bus Pentium 4’s and the Athlon64 that DDR would be unable to keep pace with the increased data demands of modern desktop MPUs, let alone their bandwidth hungry HPC & server counterparts.
Figure 1 – DRAM Core Frequency vs. Bandwidth Trends (Micron)
This is primarily the result of clocking limitations inherent to DDR. It is currently very difficult to clock DRAMs above 200MHz. In DDR, the 400MHz clock speed is accomplished by using an I/O controller which runs at 200MHz and fetches 2 bits at a time (i.e. two adjacent memory cells are read simultaneously).
DDRII achieves higher clock speeds using a given core DRAM frequency by running the I/O controller at 2x core speed with a 4 bit fetch. Thus, in DDRII-400, the core runs at 100MHz and the I/O controller at 200MHz, and 4 memory cells are read or written at a single time. These multiple reads and writes lead to longer turn around time, however, the performance loss is minimal considering the effective doubling of the bandwidth.
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