Background Reference: Charge Carrier Mobility and Ion/Ioff
Fundamentally, a microprocessor switches state as fast as the slowest stage of its pipeline. Each state of the pipeline has a stack of logic gates that the electrons must flow through before the data is ready to be latched for use by the next pipestage (see the FO4 article). In order to increase processor frequency, transistors of a given processor design must be made to switch state at a faster rate. One process neutral measurement of how fast a transistor can switch state (or rather, drive others to switch state) is the relative on-state current flow through the transistor, Ion. Higher current flow through the transistor when the transistor is switched on means that it is able to drive the next transistor in the logic stack to switch state faster. Higher Ion thus means a higher performance transistor and higher dynamic current draw when the transistor is in the active state. Conversely, Ioff measures the channel leakage current of the transistor when it is in the “off” state. The ideal transistor will then have an extremely high Ion coupled with a nearly zero Ioff. Since there are no ideal transistors, process engineers try to optimize for the maximum differential between Ion and Ioff. In case of a process technology where the Ion/Ioff ratio has several orders of magnitude differential, the process technology tweaked for an embedded processor could accept a lower Ion in order to achieve the lowest Ioff (lowest quiescent power). In case where the same process technology is tweaked for a high performance processor, Ion may be driven to the highest value possible, but if the relative Ion/Ioff ratio is maintained, then the increased Ioff means that the high performance processor would incur a higher cost of leakage power.
The goal of process technology design is then to increase Ion without increasing Ioff, or conversely, decrease Ioff without decreasing Ion. One way by which the Ion/Ioff ratio may be increased (without increasing Vt, the threshhold voltage) is to increase the mobility of the charge carriers. By increasing the mobility of the charge carriers, current could flow more easily, and the "on" current could be proportionally larger without increasing Ioff, the short channel leakage current.
Strain Engineering: Strained Silicon (mobility enhancement)
Figure 3 – Strained Silicon using SOI and SiGe Substrates
One technique that is being carefully examined and deployed to increase Ion without increasing Ioff is the use of germanium in the conduction channels to “stress” the silicon lattice and enhance channel mobility. IBM described a device structure whereby it is able to build a strained silicon channel directly on the oxide insulator (SOI) without the benefit of the SiGe buffer. Although the transistor has yet to be fully optimized, and as such is less than optimal in terms of drive current, the reduced body thickness may enable further device scaling.
High-K Gate Dielectric
The use of SiGe increases hole and electron mobility, and as a result increases transistor drive current, Ion, without increasing Ioff. However, strained/stressed silicon is not specifically targeted towards the reduction of leakage current. In general, there are two different sources of leakage, gate-oxide leakage (Igate) and short channel source-drain leakage (Ioff). While both type of leakage contribute to the overall leakage characteristic, gate-oxide leakage currently dominate the leakage equation. Theoretically (at a sophomoric level), the gate oxide is an insulator, and no current should flow through the gate oxide, regardless of the relative voltage applied. However, transistor gate oxides have been relentlessly thinned down to layers several atoms thick in pursuit of reduced capacitive loading and faster transistor switching time. As a result, electrons are now finding their way in, tunneling through the thin gate oxide. High-K gate dielectrics are currently being investigated as a solution to this problem. Traditionally, silicon dioxide (SiO2, k = 4.2) has been used as the gate dielectric. In IEDM 2003, a slew of papers were published discussing the problems and limitations associated with the use of a new high-K dielectric material, hafnium oxide (HfO2) as the gate oxide material. As the reliability and manufacturability issues for hafnium oxide are resolved, it seems likely that it will be the high-K dielectric of choice for future generations of process technology and will serve to reduce leakage current through the thin gate oxide.
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