Coverage of IEDM 2003: AMD and Intel on Day 2

Pages: 1 2 3 4 5 6

Post Mortem, Now and Near Future: AMD’s Learning Curve on 130nm and 90nm SOI

In session 11.1, AMD disclosed that its yield problems at the 130nm SOI process were due primarily to the integration of low-K materials into the process rather than SOI, as previously suspected. AMD chose to use hydrogenated silicon oxycarbide (SiCOH) for their low-K dielectrics, replacing fluorine-doped tetra-ethyl-ortho-silicate (FTEOS) as the dielectric material.

Much of the paper described the learning curve as the 130nm SOI process was slowly ramped up.

IEDM-Day2-fig1.gif - 65726 Bytes
Figure 1 – AMD’s 9 Layer Metal Stack.
IEDM-Day2-fig2.gif - 55554 Bytes
Figure 2 – Effects of Low-K Dielectric on RC Compared to FTEOS.

Here is a summary of the presentation:

  1. 130nm Opteron die size is 194 mm2, 90nm Opteron die size is 114 mm2.
  2. Over the past 2 years, process speed (130nm SOI) has been improved by 80+%, as measured by the speed of a ring oscillator (Editor’s Note: The correct percentage should be 50%, per David Wang’s update of 1/2/2004, as follows: “Ring Oscillator speed improved from 1200 to 1800 at the same leakage level, not over 2000.”). AMD used “abstract units” to give the relative speed of performance improvement. The graph shows that over the past months, the speed of the ring oscillator increased form approximately 1200 AU (abstract/arbitrary units) to over 2000 AU.
  3. AMD uses bonded SOI wafers, and while “Large Area Defects” are unavoidable in bonded SOI wafers, AMD has worked with its suppliers to carefully screen the bonded wafers. Bonded wafer defect rates are now in the low single digits.
  4. Over time, AMD has learned to optimize device gate structure for SOI, rather than simply use a transplanted bulk gate structure (bulk gate polysilicon etch). The performance improvement contributed to the overall performance improvement as noted in (2).
  5. The process stack was more complex on SOI than on bulk, and the addition of low-K materials added to the complexity.
  6. Low k defect (for new low k material, k-effective <3.0) was worse than FTEOS (k value = 3.6). The defect rate has improved over time to match rates attained using FTEOS. The three main improvements that contributed to higher yields were: Wafer Edge engineering, wafer handling and deposition control.
  7. Wafer Edge control: The metal/dielectric stack was different at the edge of the wafer, and adhesion of the stack was a problem. During certain steps of the process, pieces of the poorly adhered stack would flake off of the wafer, creating defects not only where they flaked off from, but also where they landed. Careful process control and altered wafer handling procedure greatly reduced or eliminated this type of defect.
  8. When the relative yield rates are normalized, the yields from the 130nm SOI process are now roughly equal to that of the 130nm bulk process. The yield rate is tracked on a weekly basis, and for a given week, the normalized yield rate on the 130nm SOI could even be better than that of the normalized yield rate of the 130nm bulk process.
  9. The integration of the low-K dielectric has resulted in a 15-20% reduction in the RC characteristics of the 130nm SOI process.
  10. One intriguing point was brought up during the Q&A session, although it was not directly answered by the presenter. The point was raised that the thermal conductivity of the buried oxide layer is lower than bulk silicon. The question was asked if SOI chips needed more specialized cooling solution, or if AMD has designed anything in Opteron to specifically address this issue. The presenter replied that he viewed this problem as part of the engineering challenge to move heat away from the silicon devices and off of the chip, not something specific to the Opteron processor on the SOI process.

AMD has provided selected presentation slides, which can be viewed on the Day 2 Supplement page.

Pages: « Prev   1 2 3 4 5 6   Next »

Discuss (10 comments)