Low-K (now), and High-K (maybe 4 years away)
Intel submitted a late paper in session 11, listed as 11.6 that disclosed details about its use of strained silicon in its upcoming 90nm process technology. Intel also presented papers on the use of high-K material. The promotion of both “high-K” gate dielectric and low-K (inter-layer) dielectric may be a source of confusion to non-technical readers. The quick answer is that they’re both good, and they’re both needed. The longer answer is that the high-K dielectric is needed as the gate dielectric, insulating the gate from the channel, reducing gate leakage current by orders of magnitude. At the same time, low(er)-K dielectric is needed in between the metal layers to reduce the RC delay and increase circuit speed. AMD’s presentation on its 130nm SOI process had already stated that point that although the new lower k dielectric material was initially problematic, once the problems were solved, it enabled a reduction of 15~20% in RC characteristics.
Figure 3 – Intel’s 7 Layer Metal Stack.
Figure 4 – Intel’s 50nm Gate Length in the 90nm Process Node.
The two figures above show that the low-K dielectric goes in between the metal layers, and it also shows that the gate on the 90nm process is only 1.2 nm thick.
Figure 5 – Closer View of the Gate.
As summarized in our Day 1 coverage, there are two type of leakage current: gate to body and (short channel effect) drain to source. As gate length shrinks, drain to source leakage increases. In order to reduce drain to source leakage, gate oxide thickness needs to be reduced. Thinner gate oxide allows better gate control over the channel, which can cut down drain to source leakage. However, thin gate oxide increase gate to body leakage due to tunneling effects. Here is where high-k material will play a role. An ideal high-k material provides “thin” electrical thickness and “thick” physical thickness. So, it cut down both drain to source leakage due to its “thin” electrical properties and also cut down gate to body tunneling leakage due to its “thick” physical properties.
Figure 6 – Replacing the SiO2 with High-K Gate Dielectrics Lowers Gate Leakage.
Figure 7 – Intel Process Roadmap Showing High-K Gates at the 45nm node in 2007.
Intel reported that they are confident that high-K gates will be in place by the 45nm node. However, the process is still a few years out, and plans may change. In the mean time, Intel’s 65nm and 90nm nodes will likely have relatively high leakage characteristics. Also, several other papers have reported various challenges still remain with high K gates. EE Times also has a nice summary of the same issues.
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