Intel’s Strained Silicon on 90nm
Figure 8 – Comparison of Traditional Strained-Si and Intel’s Strained-Si
Figure 9 – Picture of the NMOS and PMOS Transistors.
Intel claims that the strained approach increases drive current by 25% compared to non-strained silicon. The data on the drive currents show that there are between 6-7 orders of magnitude difference between Ion and Ioff. Intel’s approach to strained silicon was somewhat of a surprise. The traditional approach to strained silicon is to use a layer of silicon germanium to stress a thin layer of silicon. Instead, Intel disclosed that it used two different techniques to separately stress the silicon in the respective active channels in its NMOS and PMOS transistors at the 90nm node. As shown in the respective illustrations, Intel used a thin film to provide tensile stress to the channel in the NMOS device along the length of the channel. For the PMOS, Intel used epitaxially grown silicon germanium in the source and drain region to provide compressive strain also along the length of the channel to facilitate current flow. Intel claims that this approach minimizes the cost associated with the addition of strained silicon. The presenter cited a figure of 2% cost overhead, which was acceptable when compared to the improvement in the magnitude of the increased drive current.
PMOS high Vt
PMOS low Vt
NMOS high Vt
NMOS low Vt
Table 1 – Ion and Ioff for Intel’s 90nm Transistors.
One technique Intel had adopted on the 130nm process and continued on the 90nm process to attain higher performance is to use two different speed transistors. In Table 1, we show the relative Ion and Ioff currents for the two transistors on Intel’s 90nm process with strained silicon. One type of transistor is the “low Vt”, and the other is of course “high Vt”. At the 90nm process node, Intel’s low Vt transistors provide roughly 15% higher drive currents at the expense of 10X higher subthreshhold (short channel) leakage current. Most circuits would use the “high Vt” transistor, but in cases where performance is critical, and static (leakage) power is less of a concern, such as desktop Pentium 4 MPUs, low Vt transistors may be more liberally deployed on critical paths. In designs where power consumption is the highest priority, such as the Pentium M, low Vt transistor deployment may be tightly restricted.
Figure 10 – Defect Densities for Intel Manufacturing Processes
Intel claims that the defect rate (and inversely proportional to the yield rate) on the 90nm process has already been reduced to a level comparable to the lowest defect rates seen on the 130nm and 180nm process nodes. Note that the y axis is not labeled.
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