IBM’s High Performance 65 nm SOI Process Back End
Figure 9 – 10 level interconnect and different low-k dielectrics in different levels
In the back end of the 65 nm SOI process, 10 levels of Cu interconnects are used, and different low-k materials, specifically, advanced SiCOH based dielectrics, are used for different levels of interconnects. The reason that different types of low-k dielectrics are used in this 65 nm process is that SiCOH-based dielectrics are limited to certain thicknesses due to inherent tensile stress characteristics. Figure 9 shows that in the 65 nm process, a SiCOH-based dielectric layer is used in M1 through M4, a more advanced SiCOH-based dielectric is used in M5 through M8 and F-doped TEOS is used in M9 and M10. The reason that the advanced SiCOH-based dielectric is selectively used in M5 through M8 is that the interconnects in these levels are typically used for longer cross-chip routing, and these are the interconnects that most desperately needs the lowest-k dielectric available.
One intriguing aspect of the technical presentation on the 65 nm SOI process is that the reported SRAM cell size, 0.65 um2, is rather larger than the 2:1 density scaling trend would have predicted. At ISSCC 2005, design engineers from IBM disclosed that a SRAM cell on the 90 nm CELL processor uses 0.99 um2. Since Moore’s Law suggests that transistor density should improve by 2:1 in each process generation, the fact that the SRAM cell size on the 65 nm SOI process did not scale down accordingly is a cause for concern, particularly for the scalability of high performance products, such as the CELL processor. In response to questions about density scaling of SRAM cells, technical presenters from IBM stated that the SRAM cell on the 65 nm SOI process is designed for performance, and density scalability had been traded for performance. Moreover, unlike the 90 nm SOI process, the 65 nm SOI process no longer uses tungsten as a local interconnect, and the loss of tungsten may have contributed to the SRAM density scaling issue between the 90 nm and 65 nm SOI process nodes.
Finally, we observe that logic density loosely correlates to SRAM cell density, and the decrease in the scalability of SRAM cell sizes means that logic devices will likely have a similarly difficult time in following the 2:1 density scaling trend on a performance optimized process. The question remains open as how much logic density on a performance optimized process will deviate from the historical 2:1 scaling trend on this 65 nm SOI process. As a reference, we note that the 130 nm PPC970 processor has a die size of 118 mm2, and the 90 nm PPC970+ processor has a die size of 62 mm2, giving us a scaling ratio of 52.5%. We further note that the 90 nm DD2 CELL processor occupies a die size of 235 mm2, and a similar scaling ratio of 52.5% would predict the die size of the DD2 CELL processor as 123.5 mm2 on the 65 nm SOI process, while a scaling ratio of 66% would predict the die size of the DD2 CELL processor as 155 mm2 on the 65 nm SOI process. Given that the CELL processor contains high performance I/O interface circuits (Redwood and XDR2) that may be difficult to scale down to the 65 nm SOI process and the SRAM cell size on the 65 nm SOI process as reported by IBM, we presently believe that the 65 nm CELL processor will likely have a die size that is closer to 155 mm2 than 123.5 mm2.
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