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Intel’s High Performance 65 nm Bulk CMOS Process
Figure 10 – Ion versus Ioff distribution curves for Intel’s high performance 65 nm process
At IEDM 2004, Intel made the first disclosure on the performance characteristics of its high performance 65 nm bulk CMOS process [11]. At IEDM 2005, Intel provided an update in technical session 10.8 on the characteristics of it high performance 65 nm bulk CMOS process [6]. At IEDM 2004, Intel reported that the measured Idsat currents as 670/1150 uA/um for PMOS/NMOS, measured at Ioff of 100 nA/um and 1.0V. At IEDM 2005, Intel reported that through continued improvements in transistor structure and stress techniques, the respective Idsat currents have been improved to 710/1210 uA/um for PMOS/NMOS at the same conditions. Figure 10 shows the continued improvement in Idsat currents from results reported by Intel in 2004.
Intel reports the SRAM cell size in its 65 nm process as 0.57 um2. This cell size also falls short of the historical 2:1 density scaling trend for SRAM cell size – the SRAM cell size is reported as 1.0 um2 on Intel’s 90 nm process. However, since linear scaling from 90 nm to 65 nm only predicts a scaling factor of 52.1%, the degradation in density scalability of SRAM cells in Intel’s high performance 65 nm process is less than 10%4.
In its 65 nm process technology, Intel uses only 8 levels of Cu interconnects, fewer than the 10 levels of metal interconnects used in IBM’s process. The dielectric material used in this process is reported as carbon doped oxides with k value of 2.9.
4The 52.1% linear scaling factor assumes simple linear scaling in both the X and Y dimensions and can be computed mathematically from (65 * 65) / (90 * 90).
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