IBM’s Low Power 65 nm Bulk CMOS Process
In addition to its disclosure on the high performance 65 nm SOI process, IBM also disclosed detailed about its low power 65 nm CMOS process technology at IEDM 2005. IBM’s low power 65 nm CMOS process is co-developed with Chartered, Infineon and Samsung, and this process is specifically targeted for low power and low manufacturing cost. The low power process offers multiple transistor types, each with different Vt, to allow designers the flexibility to choose different types of transistors and separately optimize for low power or high(er) performance. The Idsat currents are reported for (relatively) low Vt transistors as 343/725 uA/um for PMOS/NMOS at 1.2 V and Ioff of 7 nA/um. In this process, designers can further minimize Ioff currents by using high Vt transistors with the associated loss in Idsat drive currents. The Idsat currents are reported for the (relatively) higher Vt transistors as 275/600 uA/um for PMOS/NMOS at 1.2 V and Ioff of 0.3 nA/um. The 65 nm bulk CMOS process features 9 levels of Cu interconnects and low k SiCOH dielectrics. Unlike its high performance 65 nm sibling that received a new set of low-k dielectrics for various interconnection layers, the low power 65 nm bulk CMOS shares its dielectric with the previous generation low power 90 nm bulk CMOS process for manufacturing compatibility and low cost. Finally, the embedded low power 65 nm process offers two different SRAM cell sizes of 0.676 um2 and 0.54 um2,optimized for performance and density, respectively.
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