IEDM 2005: Selected Coverage

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Intel’s Low Power 65 nm Bulk CMOS Process

At IEDM 2005, Intel also disclosed details of a new process line that is specifically targeted for low power applications. Up until the 90nm process generation, Intel has always used the same process technology to fabricate multitudes of logic devices – from the highest performance processors to its low cost embedded processors and system controller business. However, as the industry struggles with advancing the state of the art in process technology, the difficulties of simultaneously increasing drive current, decreasing leakage currents, decreasing circuit sizes, and decreasing gate and junction capacitances in each process generation has caught up even with the mighty Intel. As a result, Intel has created a separate line of process technology specifically optimized for low power operations. Intel’s low power 65nm process technology trades off Idsat drive current for considerably lower leakage currents. The presenter from Intel made the point that low power optimization requires more than merely trading off Idsat to obtain better Ioff short channel leakage current. That is, a power-optimized process must also optimize for gate leakage (Igate) and junction leakage (Ijunction) components. Without process optimization to reduce gate and junction leakage components, the process of trading off Idsat for lower Ioff becomes unattractive at lower Idsat regions, since gate leakage and junction leakage form an effectively lower bound for total leakage current. To account for transistor leakage currents including gate and junction leakage, Intel defined a cumulative leakage term ILKG, and uses it as the figure of merit in transistor leakage characteristics. Figure 11 illustrates the equation for ILKG as defined by Intel.

Figure 11 – Intel’s leakage current definition

Figure 12 – Leakage minimization trade-offs in a power-optimized process. Idsat vs. ILKG

Figure 12, taken from Intel’s presentation on its low power process, shows that in a performance-optimized process (Process I), Idsat can be traded off for lower ILKG, but below a certain level of Idsat, ILKG remains essentially constant. Figure 12 shows that by performing optimizations that targets leakage minimization, such as source and drain implantation optimization to limit junction damage and thicker gate oxides to reduce gate leakage, Idsat can be aggressively traded off to obtain lower ILKG. Figure 12 shows that with these optimizations, ILKG can be reduced by three orders of magnitude as compared to a transistor that had not been specifically optimized for low leakage. However, Figure 12 also shows that the drawback to the leakage-power-specific optimizations is that the Idsat vs. ILKG distribution curve is shifted to the left for higher Idsat values. Consequently, the leakage-power-specific optimizations are not suitable for integration to a performance-optimized process, and different processes are needed to separately target high performance or low leakage transistors.

To minimize manufacturing costs, Intel attempted to keep as much commonality between its high performance and low power 65 nm processes. Intel reports that the new power-optimized process technology uses the same equipment and toolset as the high performance 65nm process, and the two processes can run side by side within a given fabrication plant. However, the two processes are not identical in terms of design rules: M5 through M7 are slightly narrower in the low power process, and gate lengths are longer. As a result, design portability would be an issue. That is, Intel could not simply take a desktop or server processor that had been designed for the high performance 65 nm process and manufacture it on the low power 65 nm process to obtain an ultra-low power version of the same processor. Such a process port would require some minimal design effort to ensure circuit functionality and correctness on the low power process. Intel reports Idsat currents on the power-optimized process as 380/660 uA/um at Ioff of 100 pA/um and 1.2V. The SRAM cell size on the low power process is reported by Intel to be 0.68 um2. The interesting point of note is that just as SRAM cell density was traded off for performance in IBM’s high performance 65 nm SOI process, SRAM cell density was also traded off in Intel’s low power process to minimize leakage.

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