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Low Write Current MRAM: One Memory to Rule Them All
At IEDM 2005, Sony announced a breakthrough in magnetic random access memory technology (MRAM). MRAM devices are highly attractive as a potential, unified replacement memory in system-on-chip applications. Similar to non-volatile flash memory (NVRAM), MRAM does not require power to maintain data storage. However, unlike NVRAM, MRAM devices have the advantage that write speed is comparable to read speed. Furthermore, MRAM devices are not known to be constrained to a limited number of erase-write cycles. Also, one final advantage to MRAM is that MRAM storage is based on switching magnetic fields and no active silicon real estate for charge storage is needed. The disinterest in active silicon real estate means that MRAM cells can be fabricated in between the metal layers above active logic circuits, and MRAM could be an ideal candidate as local memory for any embedded processor, simultaneously replacing SRAM, eDRAM, and any embedded NVRAM.
MRAM devices are known to have three drawbacks when compared to other types of embedded memory: high write current, relatively large cell sizes, and compatibility with logic based process. The process compatibility issue means that suitable materials had to be found and integrated within the framework of the process flow of a logic-targeted process to preserve the functionality and performance of transistors on the surface of the active silicon and enable the integration of embedded MRAM cells with logic circuits. Although the process compatibility issue is a serious concern, the cell size issue for MRAM is less of a concern for embedded systems. The current generation of MRAM cells (~40 f2) are larger than eDRAM (~25 f2), and NVRAM (~4 f2), it is however far smaller than SRAM (>100 f2)5. Moreover, the fact that MRAM cells do not require the use of active silicon means the cell size issue is less of a concern, particularly when compared to SRAM, eDRAM, or NVRAM on a given design. However, the final issue of high write current needed to reverse magnetic fields remained a concern for embedded systems, since the high write current required associated costs in additional circuits and peak power consumption. Fortunately, the breakthrough announced by Sony at IEDM 2005 is precisely targeted to reduce the high write current of MRAM devices.
In technical session 19.1 at IEDM 2005, Sony presented details of a type of magnetic memory that utilizes spin torque transfer to effect the switch in magnetic fields, rather than rely on a current to switch magnetic field in the magnetic tunnel junction (MJT). Sony refers to the new MRAM device as Spin-RAM, and demonstrated a 4 kbit Spin-RAM device that was fabricated on a 180 nm process with 4 metal layers of interconnect. Sony further states that write speed as fast as 2 ns and write currents as low as 200 uA were successfully performed on the test Spin-RAM device. Also, Sony claims that the new Spin-RAM cell structure shows great promise in terms of scalability to 45 nm and future processes, and that reliability of the Spin-RAM cell has been demonstrated through more than 1012 write cycles. At IEDM 2005, Renesas Technology Corp. and Grandis, Inc. announced an agreement to develop products based on the spin torque transfer technology. The expected products, primarily microcontrollers that were previously designed with a mixture of different types and sizes embedded memory, will be designed and fabricated on leading edge 65 nm processes. Grandis and Renesas claim to have overcome the process compatibility issues, and expect that microcontrollers with embedded MRAM to possess unique advantages and features not found in comparable microntrollers and SOC devices.
5An f is a process neutral metric for area comparisons. On a 90 nm process an f is 90 nm, and on a 65 nm process an f is 65 nm. For example, on the 65 nm process, a unit of f2 is 0.065 um x 0.065 um or 0.004225 um2. An SRAM cell that occupies 0.65 um2 can also be described as 154 f2 in size.
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