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IEDM 2005 provided a wealth of technical presentations. Despite the length of this article, the coverage in this article summarized fewer than 5% of the 240 presentations given at IEDM. Other interesting technologies that were presented but not covered in this article included technology such as carbon nanotube based DRAM devices (paper 11.4), or a novel technique for assembling multiple known good dice (paper 14.4). IEDM 2005 also provided interesting updates on the latest trends. In particular, as a direct consequence of the difficulty in process scaling, process complexity and process design rules are continuing to grow unabated in each process generation, and the family of logic-optimized semiconductor processes are growing increasingly divergent to separately target performance and low power characteristics.
We thank the follow persons and organizations for their respective contributions to this brief summary of IEDM 2005:
Gary Dagastine, co-media relations director of IEDM, for providing the IEDM archives on DVD. The IEDM archives on DVD made possible quick research on previous IEDM papers. (A whole lot faster than going though IEEE Archives)
Professor Weizhong Wang of the University of Wisconsin, Milwaukee, for providing context to the numerous technical disclosures on semiconductor processes made at IEDM 2005.
Dr. Woo-Hyeong Lee of IBM, for providing his presentations slides on IBM’s 65 nm SOI process, and his time in answering additional questions.
Dr. Gary Bronner of IBM, for his insights on the discussion of area and performance trade-offs on the 65 nm SOI process.
Yuzuru Ohji of Renesas, William Almon of Grandis, and Dr. Yiming Huai of Grandis, for the discussion on the use of MRAM in Renesas’ next generation products, and the implications of MRAM proliferation in future products.
Applied Materials, for providing the informative evening seminar on scaling difficulties past the 45 nm process generation.
Copyright 2005 David T. Wang. All rights reserved.
 W. Lee et. al., “High Performance 65 nm SOI Technology with Enhanced Transistor Strain and Advanced-Low-K BEOL”, Technical Digest of the International Electron Devices Meeting, IEDM 2005, paper 3.3, pp 61-64.
 A. Steegan et. al., “65 nm CMOS Technology for low power applications”, Technical Digest of the International Electron Devices Meeting, IEDM 2005, paper 3.5, pp 69-72.
 P. Ranade et. al., “High Performance 35 nm Lgate CMOS Transistor featuring NiSi Metal Gate (FUSI), Uniaxial Strained Silicon Channels and 1.2 nm Gate Oxide”, Technical Digest of the International Electron Devices Meeting, IEDM 2005, paper 10.1, pp 227-230.
 A. Oishi et. al., “High Performance CMOSFET Technology for 45 nm Generation and Scalability of Stress-Induced Mobility Enhancement Technique”, Technical Digest of the International Electron Devices Meeting, IEDM 2005, paper 10.4, pp 239-242.
 M. Horstmann et. al., “Integration and Optimization of Embedded-SiGe, Compressive and Tensile Stressed Liner Films, and Stress Memorization in Advanced SOI CMOS Technologies”, Technical Digest of the International Electron Devices Meeting, IEDM 2005, paper 10.5, pp 243-246.
 S. Tyagi et. al., “An Advanced Low Power, High Performance, Strained Channel 65 nm Technology”, Technical Digest of the International Electron Devices Meeting, IEDM 2005, paper 10.8, late paper submission, pp 1070-1073.
 C. Chen et. al., “Stress Memorization Technique (SMT) by Selectively Strained-Nitride Capping for Sub-65nm High-Performance Strained-Si Device Application”, Digest of Technical Papers, 2004 Symposium on VLSI Technology, 15-17 June 2004, pp 56 – 57
 S. Thompson et. al., “An Enhanced 130 nm Generation Logic Technology Featuring 60 nm Transistors Optimized for High Performance and Low Power at 0.7 – 1.4 V”, Technical Digest of the International Electron Devices Meeting, IEDM 2001, pp 257-260.
 N. Rohrer et. al. “PowerPC in 130nm and 90nm Technologies”, International Solid-State Circuits Conference Technical Digest, Feb. 2004.
 P. Bai et. al. “A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-K ILD and 0.57 µm2 SRAM Cell”, Technical Digest of the International Electron Devices Meeting, IEDM 2004.
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