Cooptition: Defraying the Cost of Semiconductor R&D
On Tuesday December 6, IEDM sponsored an evening panel discussion session on the topic of the increasing semiconductor research budgets that are being devoted to solve increasingly difficult process scaling issues. The central theme of the panel discussion was that gross revenue for the semiconductor industry as a whole is increasing at a rate of 6% per year, whereas the cost of ongoing semiconductor research and development is increasing at a rate of 12.2% per year. The panelists all agreed that the rate of increase in research and development expenditure means that semiconductor process technology development is an activity that will become too expensive for all the largest individual companies.
As a result, several alliances have been formed between groups of semiconductor manufacturers to share the cost and risks associated with developing new process technologies. Currently three alliances have been formed to jointly develop leading edge process technologies and shared the associated risks and expenses. The first alliance is between IBM, Toshiba, Sony and AMD for jointly developing high performance SOI process technologies. Three papers on high performance 65 nm SOI process technologies were presented by members of this alliance in technical sessions 3.3, 10.4 and 10.5 [1,4,5]. The second alliance is IBM, Chartered, Infineon and Samsung and focuses on developing low power process technologies. One paper on the low power 65 nm bulk CMOS process technology was presented by IBM in technical session 3.5 . Finally, the Crolles 2 Alliance (after their design center in Crolles, France), consists of ST Microelectronics, Philips, and Freescale, with cooperation from TSMC, and is jointly developing high performance CMOS process technologies1.
The evening panel discussed the new models of semiconductor manufacturing, where competitive manufacturers gather in cooperation to defray the costs and risks associated in the development of leading edge process technologies. However, once the baseline process technology is developed for each process generation, the partners in each respective alliance then return as competitors in the market with the commonly developed baseline process technology. The word cooptition was coined in the evening panel discussion to describe this model of shared research and development with competitive manufacturing. The conclusion of the panel discussion suggests that the cooptition model will become more entrenched as process scaling becomes increasingly difficult and ever larger gaggles of PhD’s are needed to attack the problem.
In the discussion on the various alliances, one company is conspicuous by its absence. That company is of course Intel. As the premise of the cooptition model suggests, research and development activities in process development are becoming increasingly costly and set to become too expensive for all but the largest companies to undertake independently. Fortunately (for Intel), Intel is the one company with a war chest that is sufficiently large to continue to pay the ever increasing costs of semiconductor research and development for the immediate future.
However, it appears that even mighty Intel is not averse to joining alliances to defray the cost and risk of semiconductor process development. Unfortunately for Intel, asymmetries in the semiconductor industry seriously hinder any partnerships. A true alliance requires willing and technically capable partners that can share in the costs and risks and have similar design targets: high performance, high volume and low cost semiconductor process. Just as important, any partners must truly contribute to an alliance with Intel, rather than simply enjoying the fruits of an unequal alliance. For these reasons, Intel remains alone in the field of semiconductor R&D, while IBM is proceeding ahead with numerous alliances in process development.
1More information about the Crolles 2 Alliance can be found here.
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