IEDM 2005: Selected Coverage

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Background: The Cgate * Vdd / Idsat Metric

The trend in density scaling characteristics in each successive process generation has been codified by Moore’s Law, and the world at large has been trained to expect that the area occupied by a transistor will shrink by 50% in each successive process generation. An alternative and equivalent phrasing is twice the number of transistors in the same die area.

However, the trend in performance scaling characteristics in each successive process generation has not been similarly codified, and no “law” exists to predict process performance scaling characteristics2. Moreover, unlike the ease of using the number of transistors as the metric of density improvement, no comparable self-evident metric of similar ease exists with a common set of circuits to measure the performance characteristics for the diverse ecosystem of modern semiconductor process technologies.

Fortunately, the International Technology Roadmap for Semiconductors (ITRS) has adopted Cgate * Vdd / Idsat (CV/I) as a metric. CV/I is a process-neutral, 0th order approximation to measure transistor performance across different process generations and process technologies from different manufacturers. In the formula Cgate * Vdd / Idsat, Cgate is the junction and input capacitance of the transistor gate, Vdd is the value of the supply voltage, and Idsat is the saturation current of the transistor. For fundamental improvements in process speed, each successive process generation can decrease gate capacitance, decrease supply voltage, increase transistor saturation drive current, or any combination of the three factors.

The CV/I metric can account for changes in process technologies in terms of thinner gate oxides or shorter channel lengths, but it does not account for interconnect delays. As a result, it is best used as a 0th order approximation to measure process performance. The units for CV/I are seconds. Smaller CV/I values represent smaller transistors delay values and a faster process technology. Table 1 contains various CV/I values, taken from an ITRS document that examines the relationship between CV/I and FO4 delay characteristics [7]. Table 1 provides few sample CV/I values and a reference scale that compares the intrinsic process performance of Intel’s 180 nm and 130 nm process technologies.

Table 1 – CV/I values for Intel processes 1998–2001

2The presenters from Intel assert that intrinsic gate delay is decreasing at a rate of 0.73 per generation (in a performance-targeted process). That is, each new process generation brings new transistors whose CV/I value is 0.73 times that of the previous generation. The 0.73 rate also translates a rate of 37% increase in frequency per process generation.

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