Background: Stress Engineering
At IEDM 2005, two papers on silicon stress techniques to increase charge carrier mobility and consequently transistor drive current were presented by members of the IBM-Sony-Toshiba-AMD high performance SOI process alliance [4,5]. Specifically, Paper 10.4 was presented by a Toshiba-led team, and it explored path finding work in the applicability of turning the silicon stress knob to continue performance scaling trends on future 45 nm, 32 nm and 22 nm process generations. In contrast, Paper 10.5 was presented by an AMD-led team, and it presented work in turning the silicon stress knob on existing 90 nm and 65 nm process generations. In these two papers, 4 different silicon stress techniques are described and their effects as functions of process scaling, design difficulty and respective performance improvements are simulated, measured, and reported. The silicon stress techniques and their effects as reported at IEDM 2005 are briefly summarized below.
In IBM and Intel’s respective process technologies, Silicon Germanium (SiGe) is selectively embedded in the source and drain regions of the PMOS transistor to provide compressive stress to the conduction channel in the PMOS transistor. There are, however, subtle differences in the integration of SiGe in the respective process technologies due to differences inherent to the SOI and bulk CMOS wafers. Paper 10.5 reports that SiGe growth is extremely important to PMOS transistor performance, and a third generation SiGe integration has achieved as much as 65% improvement in Idsat current for PMOS transistors.
Compressive and Tensile Stress Liners
Figure 4 – Tensile stress liners on Intel’s 90 nm NMOS transistors, no liner on PMOS
Stress liners have been used in existing 90 nm processes, most notably at Intel. Intel was one of the first manufacturers to include the use of stressed silicon in a production process technology, and our previous coverage of IEDM 2003 illustrated that Intel’s use of stress liners in its 90 nm process technology. Figure 4 illustrates the transistor structure in Intel’s 90 nm process. Figure 4 shows that Intel used a high stress film (hereafter referred to as a stress liner) over the gate of the transistor structure to provide tensile stress in the conduction channel of the NMOS transistor. Figure 4 also shows that Intel did not use a stress liner for the PMOS transistor in its 90 nm process.
In contrast to the work presented by Intel at IEDM 2003, more recent work in stressing the silicon presented in technical sessions 10.4 and 10.5 at IEDM 2005 emphasized that the IBM-Sony-Toshiba-AMD high performance SOI process used stress liners for both the NMOS and PMOS transistors. Stress Liners are used by the IBM-Sony-Toshiba-AMD alliance to provide tensile stress for the NMOS transistor and compressive stress for the PMOS transistor. The stress lining technology is also commonly referred to as Dual Stress Liners (DSL) by members of the IBM-Sony-Toshiba-AMD alliance.
The paper for technical session 10.5 describes the implementation of the dual stress liners as follows: After the formation of the transistor structure, a compressive liner film is first deposited on the silicon wafer, and then selectively removed from the NMOS region. A tensile film is then deposited onto the silicon wafer and selectively removed from the PMOS regions. Figure 5, taken from paper 10.5, shows the use of stress liners for both the NMOS and PMOS transistors in AMD’s 65 nm process.
Figure 5 – Tensile stress liners on AMD’s 65 nm NMOS, compressive stress liner on PMOS
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