IEDM 2005: Selected Coverage

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Stress Memorization

The stress memorization technique to enhance channel was discussed in depth in a paper published in the VLSI Technology Symposium, 2004 by Chen et. al. from TSMC [8]. In the stress memorization technique, a nitride layer is selectively and temporarily deposited on top of the gate electrode to provide a high level of tensile stress to the channel in NMOS transistors. The high-tensile nitride layer is eventually removed, but only after source and drain activation and the wafer undergoes a carefully controlled poly amorphorization and recrystallization procedure.

In essence, the nitride layer acts as a stressing agent that holds the conduction channel in a stressed state. The silicon wafer is then heated and allowed to cool down in a carefully controlled annealing process. The annealing process locks in the poly silicon crystals in a state that continues to hold the stress on the conduction channel even after the original stressing agent, the selectively deposited nitride layer, is removed. The silicon is thus said to have “memorized” the stressed state.

Performance Improvements from Stress Engineering

Figure 6 – Reported improvements in Idsat from stress engineering

Figure 6 shows the improvement in Idsat reported by the AMD-led team in paper 10.5 of IEDM 2005. Figure 6 shows that by deploying all four types of stress inducing techniques, AMD was able to shift both the NMOS Idsat versus Ioff and the PMOS Idsat versus Ioff curve to the right. On average, the stressing techniques increased Idsat by as much as 53% in PMOS transistors and 32% in NMOS transistors at a given Ioff current. Equivalently, the increases on Idsat translates to an improvement of 40% in the maximum operating frequency (FMax) of an AMD Athlon64 processor at a given leakage level.

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