Process Technology Advancements at IEDM 2007

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High-K Gate Dielectric

In a previous coverage of IEDM, we noted that the various old, dependable knobs that enable transistor performance scaling in each successive process nodes were broken, and that even new knobs were turned to the maximum [1]. It was clear then that new tricks had to be found to enable the continuation of transistor performance scaling trends. One of the old knobs that is now broken is the gate-thickness knob – tOX. In essence, gate dielectric have reached the limits of minimum thickness, where any further reduction in the thickness will results in unacceptable leakage through the gate dielectric for typical circuit applications.

The solution to the gate dielectric thickness scaling issue is to replace the gate dielectric with material that can reduce gate leakage and also reduce the capacitive load equivalence. In the 65 nm and 45 nm nodes, semiconductor engineers have mostly turned to the use of nitrided oxides, where Nitrogen is incorporated into the silicon dioxide gate. The nitrided oxide is effective in limiting Boron diffusion through the gate dielectric and slightly increases the K-value of the gate dielectric. In the 32 nm node and beyond, it is expected that the nitrided oxides will be replaced with true high-K materials, such as Hafnium Silicate.

At IEDM 2007, TMSC and Fujitsu both relied on the use of nitrided oxides as the gate dielectric material of choice in their respective 45 nm process technologies [2,3]. One exception to the nitrided-oxide-at-45-nm rule is Intel, which reported its success in integrating a hafnium based gate dielectric in paper 10.2 at IEDM 2007 [4]. It should also be noted that the semiconductor alliance of IBM, AMD, Sony, Toshiba had previously announced its success in integrating Metal Gate and High-K Gate Dielectric into its 45 nm process in June 2007 at the IEEE Symposium on VLSI Technology 2007 in Kyoto, Japan [13].

193 nm Immersion Lithography

One characteristic common to all except one 45 nm process technology reported at IEDM 2006 and IEDM 2007 is the use of 193-nm Immersion Lithography [2,3,4,5,6]. As TSMC summarized in its paper, ArF 193-nm lithography has approached the theoretical limit of scalability at the 55 nm node. It was therefore a common consensus that immersion lithography is needed for the 45 nm node, and double patterning using 193-nm immersion lithography will be needed at the 32 nm node [7]. However, Intel once again defied common wisdom and developed its 45 nm process technology without the use of immersion lithography. Since the cost of immersion lithography machines have been reported to be up to $28 million per unit, Intel’s success in developing a high performance 45 nm process technology on bulk silicon without requiring the use of immersion lithography should give it a cost advantage at the 45 nm node over its competitors.

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