Intel’s Process Technology Presentation Team Returns
In 2006, Intel’s semiconductor process engineers were conspicuously absent from IEDM. In the eight years immediately preceding 2006, Intel’s semiconductor process engineers had presented conference papers on its leading edge process technology at IEDM every year. Intel’s absence at IEDM 2006 was therefore intriguing and puzzling. However, subsequent to IEDM 2006, Intel released some details on its 45 nm process technology through press announcements and presentations on its website in January 2007 . Then, Intel also publicized some details about its upcoming 32 nm process technology in September 2007, again through the mechanism of press announcements augmented by presentations on its own web site . It appears therefore that Intel has chosen to shift the announcement of its semiconductor process achievements from the more technical forum of IEDM to the more mainstream forum of press announcements.
At IEDM 2007, Intel has resumed presentation of its process technology at IEDM by presenting a paper on its 45 nm process technology in session 10.2. One issue worthy of note is that even though initial details of its 32 nm process technology were released through press announcements in September 2007, Intel did not present a conference paper on its 32 nm process technology at IEDM 2007.
In session 10.2 at IEDM 2007, Intel presented a paper titled A 45 nm Logic Technology with High-K+ Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193 nm Dry Patterning and 100% Pb-free Packaging . In this paper, Intel presented details on its 45 nm process technology that, on paper, could not be matched by any other 45 nm process technology presented at IEDM in 2005, 2006 or 2007. Aside from the achievement of successfully integrating Metal gate-electrode, (High-K) Hafnium-based gate-dielectric, and the use of dry 193-nm lithography, Intel also managed to achieve record NFET and PFET drive currents – 1360/1070 uA/um at 100 nA/um Ioff and 1.0V Vdd – that were not matched by other 45 nm process technologies thus far presented at IEDM. In particular, the impressive 51% improvements in PFET drive current from its 65 nm process technology should enable Intel to continue to enjoy the triple crown of smaller die size, faster and lower power circuits for designs that are ported to the 45 nm and specifically accounts for the shift in relative NFET and PFET drive current improvements.
Overall, Intel’s 45 nm process technology appears to be an enormously impressive technology that should enable it to continue its role as the dominant semiconductor manufacturer of the present time.