Process Technology Advancements at IEDM 2007

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TSMC Storms IEDM

Fed by the growth of the fabless semiconductor industry and its leading role in this industry, TSMC demonstrated the its growth from a follower in the semiconductor industry to become one of the leaders of the industry by presenting not just one, but two papers on its R&D efforts into leading edge process technology at IEDM 2007.

In session 10.1, TSMC presented its 45 nm process technology, utilizing the 193-nm ArF immersion lithography and nitrided oxides as the gate dielectric. TMSC demonstrated NFET/PFET drive current performance of 1200/750 uA/um I_dsat at 100 nA/um I_off and 1.0V V_dd. Despite the lower reported drive currents relative to Intel’s 45 nm process technology, TMSC was able to – perhaps illustrating the capability of the 193-nm immersion lithography – attain finer geometries relative to Intel’s 45 nm process technology. For example, TSMC reported physical gate length of 30 nm relative to Intel’s report of 35 nm gate length, and TSMC further reported that its 45 nm process is able to support SRAM cells sizes ranging from 0.202 um2 to 0.324 um². Specifically, TSMC reported a functional 32 Mb SRAM test chip with cell size of 0.242 um². This reported cell size is substantially smaller than the SRAM cell size of 0.346 um² reported by Intel for its 45 nm process technology.

In session 10.6, TSMC further presented its R&D efforts into 32 nm low-power process technology. Significantly, the 32 nm process technology presented by TSMC is billed as a low-power process technology, achieving drive currents of 700/380 uA/um at 1 nA/um and 1.1V V_dd. This technology also uses a thicker (1.6 nm, instead of the 1.25 nm reported on the 45 nm process) nitrided oxide as its gate dielectric. Therefore, this process technology is presently not suitable for lower-transistor-count, fast transistor-state-transition applications. However, for designs (even high performance ones) that require enormous transistor count and relatively lower transistor-state transition requirements, this low-power 32 nm process with reported SRAM cell size of 0.15 um² can enable incredible products in the pipeline now. Specifically, FPGA’s GPU’s and GPGPU’s can well benefit from the low-power, high-density characteristics of TSMC’s 32 nm low-power process.

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