Process Technology Advancements at IEDM 2007

Pages: 1 2 3 4 5 6 7

Acknowledgements

We would likes to thank the following persons that contributed to this article.

Gary Dagastine, co-media relations director of IEDM, for providing the IEDM 2007 Technical digest and for his general assistance.

Professor Weizhong Wang of the University of Wisconsin, Milwaukee, for providing, to this writer, context to the numerous technical disclosures on semiconductor processes made at IEDM 1998, IEDM 2007, and every IEDM in between.

Dr. Krishnan Kailas of IBM T.J. Watson Research Center, for providing context to the presentations made at Symposium on VLSI Technology, 2007.

Dr. Philip Ferolito of MetaRAM, for providing insight into the importance of NBTI in contemporary semiconductor devices.

Copyright

Copyright 2007, David T. Wang, Ph.D., All rights reserved.

References

[1] Wang, D., “IEDM 2005: Selected Coverage”, http://www.realworldtech.com/page.cfm?ArticleID=RWT123005001504&p=3
[2] Cheng, K. et. al, “A Highly Scaled, High Performance 45nm Bulk Logic CMOS Technology with 0.242 µm2 SRAM Cell”, Technical Digest of the International Electron Devices Meeting (IEDM), 2007, paper 10.1.
[3] Miyashita, T. et. al. , “High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology”, Technical Digest of the International Electron Devices Meeting (IEDM), 2007, paper 10.3.
[4] Mistry, K. et. al., “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging”, Technical Digest of the International Electron Devices Meeting (IEDM), 2007, paper 10.2.
[5] Nii, H. et. al., “A 45nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL”, Technical Digest of the International Electron Devices Meeting (IEDM), 2006, paper 27.2.
[6] Narasimha, S. et. al., “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography”, Technical Digest of the International Electron Devices Meeting (IEDM), 2006, paper 27.3.
[7] Wu, S. et. al., “A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM”, Technical Digest of the International Electron Devices Meeting (IEDM), 2007, paper 10.6.
[8] LaPedus, M. “Lithography vendors prep for the next round“, http://www.industrialcontroldesignline.com/showArticle.jhtml?articleID=190302908&queryText=lithography
[9] Intel 45 nm Technology Presentation. http://www.intel.com/technology/45nm/index.htm?iid=tech_arch+body_45nm
[10] Intel Press Release, “Intel Demonstrates Industry’s First 32nm Chip and Next-Generation Nehalem Microprocessor Architecture”, http://www.intel.com/pressroom/archive/releases/20070918corp_a.htm?iid=tech_arch_32nm+body_pressrelease
[11] IBM press release “IBM Alliances Deliver Easier Path to Next Generation Semiconductor Products”, http://www-03.ibm.com/press/us/en/pressrelease/22858.wss
[12] JEDEC 2007 meeting schedule, http://www.jedec.org/service_members/Meetings/07Sch.cfm
[13] Chudzik, M., et. al. “High-Performance High-K/Metal Gates for 45nm CMOS and Beyond with Gate-First Processing”, Technical Digest of the IEEE Symposium on VLSI Technology, 2007, Kyoto, Japan, Session 11A-1.
[14] Park, Y., “Fully Integrated 56 nm DRAM Technology for 1 Gb DRAM”, Technical Digest of the IEEE Symposium on VLSI Technology, 2007, Kyoto, Japan. Session 10B-4.

Pages: « Prev  1 2 3 4 5 6 7  

Discuss (11 comments)