Process Technology at IEDM 2008

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Modern Process Technologies Comparison

As discussed in one of David Wang’s first articles on IEDM, the Cgate * Vdd / Idsat metric is used as a process neutral, 0th order approximation of transistor performance. While data for Cgate is not available for modern processes, presentations from IEDM and VLSI provide the voltage (Vdd) and drive current (Ion at 100nA/um Ioff). This data can be used to calculate a simple metric, the voltage adjusted drive strength, for transistor performance.

Figure 17 below shows NFET (X-axis) and PFET (Y-axis) performance for modern high performance logic technologies. The values are calculated as 1000 * Vdd / Ion; the large constant (1000) was chosen to ensure that the values were roughly in the neighborhood of 1. Smaller values indicate smaller delay and hence faster transistors. Higher performing technologies are in the upper right corner, while the slower ones are in the lower left. Processes using a high-k/metal gate stack are denoted by a square marker, while conventional process technologies use a diamond marker. Each company is picked out in a different color, blue for Intel, green for IBM and its various alliances, red for TSMC, orange for Fujitsu and brown for TI.

IBM’s 45nm SOI paper reported drive strength at 200nA/um Ioff, so the author made adjusted estimates for AC drive current at 100nA/um Ioff; DC drive currents would be lower still due to the self-heating effects.

Update: Figure 17 has been updated to include the new performance numbers identified by our readers, and our analysis has been updated a bit as well.

Figure 17 – High Performance, Voltage Adjusted, Transistor Drive Strength at 100nA/um Ioff

Unsurprisingly, the 32nm processes from IBM on SOI and Intel have the best transistor performance by a wide margin and with almost identical results for NMOS, and 7% better PMOS performance for Intel. This suggests that design teams from Intel, IBM and AMD should be close to parity for their basic building blocks. That being said, Intel will be in production with 32nm in late 2009, a year ahead of IBM and AMD. That should translate into a modest performance advantage as Intel will have the benefits of a year’s worth of high volume manufacturing to tweak their process, but that is very difficult to quantify.

IBM’s 45nm SOI process with high-k dielectrics and metal gates is very impressive, nearly matching the performance for the high performance 32nm processes. However from the description was more research oriented and will probably never go into production. Surprisingly, Intel’s older 45nm high-k/metal gate process stands the test of time relatively well. It is unexpected that Intel’s performance at 45nm would roughly match the two more foundry oriented 32nm high-k/metal gate processes for NFET performance and exceed both for PFET speed.

IBM and TSMC both demonstrated quite respectable performance for their 32nm bulk processes, showing substantial improvement over conventional 45nm technologies, but still lagging behind high performance microprocessor oriented processes. IBM and TSMC are closely matched with slight differences, TSMC has better performance for PFETs, but slightly worse NFET performance. Unfortunately, the drive current data for TSMC’s 28nm process is unavailable (this author failed to copy the data from TSMC’s presentation, so anyone with that information would be thanked for sharing), but the performance will be very similar to the 32nm node; a ‘half node’ does not substantially improve transistor performance.

Figure 18 shows two density metrics for various process technologies; contacted gate pitch for logic along the X-axis and SRAM cell size for storage along the Y-axis. Logic and storage density are highest in the upper right corner and lowest in the lower left. The markers and colors used are similar to those in Chart 2, with the exception that Toshiba is represented by brown. Data for IBM’s 45nm SOI process with a high-k/metal gate stack is unavailable, so results for a 45nm SOI process with a conventional gate stack (from an older IEDM 2006 paper) are shown instead. Two process technologies (IBM’s 32nm SOI and TSMC’s 32nm) have virtually identical density which made displaying them a bit tricky – the two points are picked out by the red square inside a green square in the upper right. Data for TI’s 45nm process is unavailable.

Figure 18 – Logic and SRAM Density for High Performance Technologies

As expected, there is a very clear difference between the density of 45nm and 32nm technologies – demonstrating the unarguable progress of Moore’s Law. Comparing TSMC’s reported 32nm and 28nm metrics also gives a sense of the advantage of a ‘half node’. While the drive strength and frequencies won’t improve, the density does improve noticeably.

There is also a visible disparity between the MPU and ASIC oriented technologies for SRAM density. The ASIC processes tend to have denser SRAM arrays, likely because MPU oriented manufacturers like Intel and IBM optimize more for performance – presumably obtaining lower access times for their SRAMs at the cost of extra area per cell. Additionally, MPUs run at far higher frequencies – a low latency SRAM array at 3-6GHz is an entirely different story than a low latency array operating at 0.5-1GHz.

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