Process Technology at IEDM 2008

Pages: 1 2 3 4 5 6 7 8 9 10 11 12

Summary

IEDM is a massive conference with dozens of parallel tracks to choose from. This article covers only a small subset of the presentations, focusing specifically on the next generation of logic technologies.

The theme of these presentations was the transition to a high-k and metal gate transistor stack. That trend will continue on into the future, as new materials with superior dielectric characteristics are evaluated. The current material of choice, HfO2 has a theoretical k-value of 25, but in the real world, it appears closer to 20. At IEDM 2007, SEMATECH demonstrated that HfTiSiON (k~40) could be successfully integrated into transistors and would provide further EOT scaling for 32nm or 22nm [7]. Longer term, there are materials with incredible k-values well over 1000 (e.g. lead zirconate titanate) but the difficulty lies in identifying materials that are compatible with silicon and can survive the necessary steps in manufacturing.

New higher-k materials are only one, rather obvious, area of interest. The topics covered at IEDM are overwhelming – alternative materials, source/drain engineering, FinFETs and alternative transistor architectures, quantum devices, MEMS, non-volatile storage, just to name a few. One other theme is that keeping Moore’s Law alive is increasingly complicated and companies will have to pursue a wide range of options to stay on target. Perhaps future articles will begin to explore some of the more likely techniques for the near term.

Acknowledgements

We would like to thank a number of people who helped make this article possible:

  • Gary Dagastine, who provided the DVD proceedings from IEDM 2008.
  • Dr. Scott Thompson of University of Florida, for some excellent discussions of logic technologies, lithography and transistor stacks.
  • Dan Hutchinson of VLSI Research for a discussion of overall industry trends.
  • Representatives of Global Foundries, IBM, Intel and TSMC for answering questions and providing various papers and presentations.
  • Stefan Wurm, Paul Zimmerman and Erica McGill of SEMATECH and Ryan Young of ASML for their insights into double patterning lithography options.
  • And anyone else who has contributed to this article.

References

[1] Hutchinson, Dan. “The R&D Crisis”, VLSI Research, 2005.
[2] Ronse, K. “Lithography for the 22nm Node”, Short Course on 22nm CMOS Technology at the International Electron Devices Meeting (IEDM), 2008.
[3] M. Chudzik, et. al. “High-Performance High-K/Metal Gates for 45nm CMOS and Beyond with Gate-First Processing”, Technical Digest of the IEEE Symposium on VLSI Technology, 2007, p. 194.
[4] X.Chen, et. al. “A Cost Effective 32nm High-K/ Metal Gate CMOS Technology for Low Power Applications with Single-Metal/Gate-First Process”, Technical Digest of the IEEE Symposium on VLSI Technology, 2008, p. 88.
[5] C. Auth, et al. “45nm High-k + Metal Gate Strain-Enhanced Transistors”, Technical Digest of the IEEE Symposium on VLSI Technology, 2008, p. 128.
[6] H.T. Huang et al. “45nm high-k/metal gate CMOS technology for GPU/NPU applications with highest pFET performance”, Technical Digest of the International Electron Devices Meeting (IEDM), 2007, p 285.
[7] P. Sivasubramani, et al. “Aggressively Scaled High-k Gate Dielectric with Excellent Performance and High Temperature Stability for 32nm and Beyond”, Technical Digest of the International Electron Devices Meeting (IEDM), 2007, p 543.

Pages: « Prev  1 2 3 4 5 6 7 8 9 10 11 12  

Discuss (26 comments)