Process Technology at IEDM 2008

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Gate First or Gate Last

Everyone agrees that high-k/metal gates are needed for CMOS to continue scaling effectively. However, there is some debate between the companies that have made the leap to high-k/metal gates, as to the best technique for creating the gate stack. There are two approaches used – gate first and gate replacement (or gate last). Intel is the main commercial advocate of gate replacement, while the rest of the industry appears to be using gate first techniques.

Intel’s 45nm process has already been analyzed by various reverse engineering firms, while gate first 32nm processes have yet to be thoroughly and publicly examined. As a result, the actual mechanics for gate first are not as well documented as for gate replacement. Quite a few of the techniques used in the latter can apply to gate first processes (e.g. the first interface layer between the silicon substrate and the high-k dielectric), while others will not.

Gate first is relatively similar to the process flow for existing SiON dielectic and polysilicon gate stacks. The high-k halfnium-based dielectric and a metal electrode material are deposited (instead of traditional materials), forming the gate before the source and drain ion implantation and subsequent annealing. One of the challenges of a gate first approach is finding a transistor stack that can survive the high temperatures (over a thousand degrees C) used in annealing and is also compatible with strain techniques. Proponents of gate first claim it is simpler overall and more scalable for future nodes.

A gate replacement process first forms a SiO2 or SiON interface between the silicon substrate and the high-k dielectric (HfO2 for Intel’s 45nm process). Then a thin protective interfacial layer of metal is deposited above the dielectric (Intel uses TiN for PFETs and TiAlN for NFETs), followed by the temporary polysilicon gate. The next steps are forming the source and drain, salicidation and depositing the contact etch stop and first inter-layer dielectric. At this point, the polysilicon gates are removed and substantially more metal is added to the interfacial layers to complete the metal gates.

This entire process is more complex than the gate first technique, but gate last has several claimed advantages. First, separate PMOS and NMOS metals can be used (instead of a single metal which is usual for gate first), allowing for greater optimization. Also, the two metals are not exposed to high temperatures, simplifying material selection. Lastly, Intel claims that the polysilicon gate removal can actually be used to enhance strain techniques thereby increasing drive currents.

Double Patterning Lithography is Critical

As process geometries continue to shrink over time, lithography has become increasingly challenging since there are no production worthy alternatives to 193nm ArF light sources. This leaves two alternatives for improving resolution: decreasing the k1 factor or increasing the numerical aperture (NA) [2].

Last year, almost every manufacturer (save Intel) announced a move to immersion lithography at the 45nm node to achieve the resolution needed for critical features. Immersion lithography using water increases the numerical aperture (NA) to 1.44 (air has NA=1), effectively improving resolution by one generation and carrying the industry from 65nm to 45nm. Intel ultimately skipped immersion at 45nm; it would have required new ‘wet’ lithography tools, and also raised yield concerns. Instead they chose to pursue double patterning lithography, which re-uses existing ‘dry’ tools and had already been deployed at 65nm for critical layers.

Figure 1 – 32nm SRAM Cell, Standard Single Exposure Lithography

To achieve the desired feature sizes for 32nm the industry wide consensus is that double patterning in conjunction with immersion lithography is needed. One paper from Toshiba and NEC clearly shows the unsuitability of a standard single exposure process. Figure 1 above is an SEM image of a 0.124um2 SRAM cell that exhibits both gate to gate (A) and contact-bar to contact-bar (B) shorts. In contrast, Figure 2 below shows the benefits of double patterning for several similarly sized SRAMs drawn with much more clearly defined gate end caps and no visible defects.

Figure 2 – 32nm SRAM Cells, Double Exposure Lithography

Fortunately, double patterning re-uses existing lithography tools and is rather less disruptive than immersion lithography (in most cases). It does add cost since additional steps are required (thereby reducing throughput), and can have yield impacts if overlay issues are not correctly handled. Of course, the next question is what additional techniques will be needed at 22nm in the future…

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