IBM’s 45nm SOI
In session 27.6, the Silicon-On-Insulator alliance of IBM, Freescale and AMD reported work on a 45nm process with high-k/metal gates. This paper focused on demonstrating improvements in gate scaling with the new transistor stack, rather than on presenting a production ready process. A prior paper at VLSI had shown increased drive currents, but did not demonstrate gate scaling .
Strategically this work serves as a vital learning vehicle for future process technology. The three partners presented a 32nm paper at VLSI 09 (discussed later) that focuses on a production worthy 32nm SOI process with high-k/metal gates. The abstract for this paper sounds promising with exceptionally high reported drive currents and a very compact SRAM cell in a small 16Mb array.
The presentation at IEDM 2008 discussed a 45nm process using a gate first approach to a high-k/metal gate stack, with embedded source and drain SiGe and compressive stress liners for PFET performance. Existing tensile stress liners are used for NFETs.
Figure 3 – Ion vs. Ioff curves for IBM’s high performance 45nm SOI process
Drive currents are shown in Figure 3 above. Reported AC drive currents are 1632/1192uA/um at 200nA/um Ioff and 1.0Vdd; these are shown as solid black lines in Figure 3. DC drive currents are lower due to the self-heating effects of SOI and were reported as 1485/1135uA/um at at 200nA/um Ioff and 1.0Vdd.
Experimental and simulation data showed that the capacitance penalty from scaling EOT down from 1.4nm to 1.2nm is cancelled by reducing Lgate to 25nm. Simulation results further showed that to reduce the EOT to 1.0nm (for a future 22nm process), a 23nm Lgate would be needed.
Gate pitch was reported as 190nm and neither SRAM nor the interconnect stack were discussed in the paper – signs that this is more of a research work than a production candidate.