Process Technology at IEDM 2008

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IBM’s 32nm Bulk

In session 27.3, the Common Platform alliance disclosed details of a general purpose, high performance bulk 32nm process intended for mainstream applications such as consumer products, graphics and other computer peripherals. The Common Platform manufacturing partners are IBM, Chartered and Samsung and development partners have expanded to include Infineon, Freescale, ST Microelectronics and Toshiba.

This marks IBM’s return to the world of high performance bulk silicon; while IBM and the common platform have reported results for low power bulk processes, since 130nm most high performance IBM processes used SOI.

The 32nm process uses a single metal, gate first flow as earlier described at VLSI 2008 and builds on prior work by incorporating four stress techniques for increased performance [4]. On the NFET side, stress memorization (SMT – not to be confused with Simultaneous Multi-Threading) and tensile stress liners are used to increase performance, while PFETs are improved with embedded source and drain SiGe, and compressive stress liners. The gate effective oxide thickness was scaled down to 1.2nm and 1.4nm for NMOS and PMOS transistors, somewhat thicker than the other 32nm processes presented at IEDM.


Figure 4 – Ion vs. Ioff curves for IBM’s high performance 32nm bulk process

Ion and Ioff curves reported for this process are shown above in Figure 4 and NMOS/PMOS drive currents are reported as 1250/855uA/um at 100nA/um Ioff and 0.9Vdd. At the same Vdd and lower leakage conditions of 10nA/um, performance is 1050/650uA/um., while at the lowest leakage current level of 1nA/um performance is 855/550uA/um.


Figure 5 – 0.157um2 SRAM cell for IBM’s high performance 32nm bulk process

Previous process nodes had demonstrated less than ideal SRAM scaling, due to leakage constraints on shrinking transistor feature sizes. The high-k/metal gate stack removes those constraints and SRAM cell size is reported as 0.157um2. This is a 0.5x area shrink relative to the previous generation; although no large array results were presented (in contrast to TSMC and Intel). The SRAM cell is shown above in Figure 5 and demonstrates very clearly defined end caps, likely the result of double patterning. The contacted gate pitch, a key metric that impacts logic density was reported as 126nm.

The hierarchical interconnect stack reported shrinks the metal 1 layer by 0.7X and adds a new 4x metal layer that dramatically reduces wire resistance at the same capacitance. An extremely low-k interconnect dielectric (k~2.4) is used to insulate the metal wiring.

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