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Intel’s 32nm Bulk
Intel’s leading edge process technology development team returned this year, with a paper on their high performance 32nm bulk logic process technology in session 27.9. This paper was submitted late to IEDM; whether the delay was due to competitive concerns or simply scheduling and data acquisition is unclear.
Intel’s 32nm process is the second generation of their gate replacement flow for high-k/metal gates, continuing the use of two different metals for PMOS and NMOS gates. Intel currently favors a gate last approach, because it achieves higher drive currents through stress optimization. In a prior paper, Intel claimed that a gate last flow enhanced the benefits of embedded source and drain SiGe and enabled separately optimizing NMOS and PMOS, resulting in a substantial boost to PMOS drive currents .
This is the first node where Intel has used 193nm immersion lithography. At 45nm most of the industry switched to immersion, but Intel was able to use double patterning at the critical layers instead. As noted previously, at 32nm both double patterning and immersion seem to be necessary.
Figure 6 – Ion vs. Ioff curves for Intel’s high performance 32nm process
Intel reported record drive currents in their presentation, again surpassing all other manufacturers at IEDM, although by narrower margins than last year. As the Ion vs. Ioff curves show, Intel’s paper reported drive currents of 1.55/1.21mA/um, operating at 1.0Vdd with 100nA/um Ioff; a 14% and 23% improvement over the prior generation. Linear drive currents (distinct from the saturated currents typically reported) improved by 19% (NMOS) and 11% (PMOS) over 45nm.
Intel’s presentation at IEDM actually had slightly better performance than the paper (which had been submitted several months before). Their presentation claimed PFET drive current as 1.31mA/um at 100nA/um Ioff and approximately 1.1mA/um at 10nA/um Ioff (as eyeballed by the author). Additionally, the linear drive currents were claimed as 0.228mA/um for both NFETs and PFETs, representing improvements of 19% and 28% respectively over the prior generation.
Figure 7 – 0.171um2 SRAM cell for Intel’s high performance 32nm process
Intel reported a 32nm SRAM cell size of 0.171um2, which is used to fabricate a 291Mb test chip. A schmoo plot for the SRAM test chip showed 3.8GHz operation at 1.1V. This SRAM cell is 0.494x the size of the prior generation, a scaling improvement likely due to the adoption of immersion lithography. The SRAM cell is shown above in Figure 7. Intel also reported the smallest contacted gate pitch to date, 112.5nm, ahead of competing 32nm processes and TSMC’s 28nm process.
Figure 8 – Cross section of Intel’s interconnect stack, M1-8
Intel’s 9-layer Cu interconnect stack is shrunk relative to 45nm, but otherwise the same. The lowest 3 levels are scaled to the contacted gate pitch, and metal-9 pitch is 19.4um and will be used for power distribution and gating. M9 is not shown in the figure above, as it would dwarf all other layers.
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