Process Technology at IEDM 2008

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TSMC’s High Performance 32/28nm

The paper submitted for session 28.2, describes TSMC’s high performance 32nm process. However, the presentation given by Dr. Diaz de-emphasized the 32nm node and instead focused on the ‘half shrink’ to 28nm as the primary process targeting high performance applications such as GPUs, FPGAs and some mobile devices. This is consistent with many reports in the media that have indicated key partners are favoring 28nm over 32nm. Unfortunately, TSMC declined to make their presentation (including information on 28nm) available, despite showing it to an audience of over 200 engineers from rival firms, customers and partners.

TSMC’s 28nm process implements a gate first, high-k gate/metal-gate with embedded SiGe, and nitride stress liners, both of which increase NMOS transistor performance. This appears to build on more research oriented work done at the 45nm generation that showed successful integration of a gate first approach with traditional stress techniques and attractive PMOS drive currents [6].

The second generation of TSMC’s 193nm immersion lithography (NA=1.35) was used for all critical layers. Resolution enhancement techniques were also deployed including assist features, model-based OPC and attenuated phase-shift masks.

Figure 9 – Ion vs. Ioff curves for TSMC’s high performance 32nm process

TSMC reported high performance drive currents (nmos/pmos) for 32nm, as shown in Figure 9 above are 1340/940uA/um and 100nA/um Ioff leakage current at 1.0Vdd and 980/650uA/um with 100na/um Ioff at 0.85Vdd. Figure 10 below shows the trade-off of NMOS and PMOS drive strength against gate length at a fixed leakage current of 100nA/um. TSMC also reported fabrication of high Vt devices optimized for the lowest power possible. Drive currents of 1020/700uA/um were achieved with 1nAu/um leakage currents at 1.0Vdd.

Figure 10 – Lgate vs. Ion for TSMC’s high performance 32nm process

TSMC showed a high density, 0.15um2 SRAM cell that was used in the fabrication of a 2Mb SRAM test chip on their 32nm process. For the 28nm process, the SRAM cell size is reported as 0.13um2, although there were no array level results presented. Figure 11 below shows a SEM of the 32nm cell after gate etching, also showing signs of double patterning. TSMC’s contacted gate pitch, which tends to determine logic density, was reported as 130nm for the 32nm process and 117nm for the 28nm process. TSMC’s interconnect stack uses up to 10 layers of Cu interconnect with an extremely low-k (<=2.55) dielectric, decreasing metal capacitance by approximately 30% over 45nm.

Figure 11 – 0.15um2 SRAM cell for TSMC’s high performance 32nm process

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