Process Technology at IEDM 2008

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Intel’s Low Power 45nm

The first process paper from Intel described a variant of their 45nm bulk process which is optimized for System-on-a-Chip and low power applications. Historically, Intel has presented these low power processes one year behind the main high performance process.

This paper is the first low power process to integrate a high-k/metal gate stack and has an impact similar to Intel’s first 45nm disclosure last year. The performance results are unmatched by any other low-power processes to date and will set the standard for future work in this area.

Intel’s low power process shares many characteristics with the high performance 45nm process. Both use a gate last or gate replacement technique for the high-k/metal gate stack, with two different metals for PFETs and NFETs and rely on strain techniques to increase drive currents. Physically, both use 1.0nm EOT and 160nm contacted gate pitch. The gate length for the low power process is increased to 40nm (relative to the high performance process) to reduce power consumption, and Vdd is raised to 1.1V. The prior generation 65nm low power process featured 220nm contacted gate pitch, 1.7nm EOT and 55nm Lgate.

Figure 12 – Ion vs. Ioff for Intel’s low power 45nm process

Ion vs. Ioff curves are shown in Figure 12 for NMOS and PMOS; drive currents are reported as 1080/860 uA/um at Ioff=1na/um and 1.1Vdd. Trench contacts and contact fill material optimization were used for strain engineering on NMOS devices. PMOS performance was enhanced with embedded SiGe films (30% Ge content) and the replacement metal gate process. Additional optimizations were used to minimize junction leakage.

Intel also fabricated high voltage I/O transistors, which showed significant benefits from the high-k/metal gate stack. The PMOS and NMOS drive currents were 0.62/0.52mA/um at 1.8V and 100pA/um Ioff. The PMOS results are modestly improved (17%) over a SiON/poly gate. However, the improvement in NMOS drive current is tremendous – 57%, mirroring the improvement seen in general logic transistors when Intel moved to the high-k/metal stack (51%).

Since Intel’s low power process is optimized for system-on-chip applications, a variety of other features were engineered for this process. Specific attention was drawn to analog/RF features such as resistors, capacitors, varactors, diodes and inductors.

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