Toshiba and NEC’s 32nm
A paper by Toshiba and NEC discussing their joint work on a 32nm process was a late addition (along with Intel’s 32nm paper) to the IEDM program. Like the IBM, Freescale and AMD paper this did not focus on a production ready process, but highlighted certain achievements and made some interesting observations.
The paper described a cost and density optimized 32nm process with a gate first high-k/metal gate stack. Unlike other manufacturers though, Toshiba and NEC eschewed double patterning and their process is being realized with single exposure 193nm immersion lithography.
Double patterning was evaluated, but was determined to be a poor choice due to defect density issues caused by increased process dust and the strict overlay requirements. Data from a prior process node was presented that showed defect density increasing by 25% for double patterning versus single exposure lithography. Nonetheless, standard single exposure techniques cannot provide the resolution necessary for the desired SRAM size and gate density, as illustrated by Figure 1 (on page 2) which showed severe shorting problems in SRAM cells printed with single exposure lithography.
Instead, Toshiba and NEC turned to custom illumination techniques to increase resolution. Custom illumination achieves greater resolution by improving the k1 factor in Rayleigh’s Equation, typically by emitting light from quadropoles or an annulus. Toshiba and NEC did not disclose the exact illumination conditions, but reported that their techniques improved line width roughness by 45%. Additionally, bent gate cells were used for SRAM, which decreased Vt mismatch by 8% due to the larger gate area. Using these techniques and a 4-layer Cu interconect stack with ultra low-k interconnect dielectrics, Toshiba and NEC were able to fabricate a 0.124um2 SRAM macro (the densest reported to date), that is shown below in Figure 13.
Figure 13 – 0.124um2 SRAM cell for Toshiba and NEC’s high density 32nm process
Ultimately, Toshiba and NEC reduced the cost/function by 50% in their 32nm process, compared to the previous 45nm generation and a standard cell gate density of 3650K gates/mm2. They claim that their single exposure custom illumination techniques achieve the same density as double patterning but with 9% lower cost due to fewer process steps and improved defect density. Additionally, the transition from poly-silicon/SiON gates to high-k/metal gates improved costs by 8% by reducing Vt mismatch and increasing density. The net result is a 16% gain relative to a hypothetical double patterning and poly-silicon/SiON solution and a total improvement of 50% relative to the prior generation.
The presentation did not discuss transistor physical characteristics such as Lgate, Tox and drive currents were not reported, as efforts on 32nm appear to be ongoing. We look forward to seeing more complete results in the future.