VLSI 09 Update: IBM’s 32nm SOI
The last paper we will discuss was not actually delivered at IEDM, but rather the 2009 VLSI Symposium in Kyoto, Japan. VLSI encompasses both a Technology track, which is akin to IEDM and also a Circuits track which is comparable to ISSCC. In many respects, it serves as the Eastern equivalent to those two conferences, providing a local venue for many of the key semiconductor firms which are located in Asia.
In paper 7.3 at VLSI, IBM, Global Foundries and Freescale described their 32nm high performance SOI process, which built upon the 45nm work disclosed at IEDM in session 27.6. The two most prominent applications for this process technology are the high performance microprocessors designed by IBM and AMD. The paper describes an immersion lithography process, and the appearance of the SRAMs almost guarantees that IBM is using double exposure techniques as well.
IBM’s 32nm SOI process uses a gate-first high-k/metal gate stack, as with their prior work from IEDM and VLSI. The new gate stack enabled scaling Tinv down to 1.2nm, and Lgate to 26nm while maintaining the same gate capacitance as a poly gate stack with dimensions of 2.0nm and 35nm respectively. Embedded SiGe improves the drive currents for PFETs, and dual stress liners enhance both PFET and NFET mobility. Relative to prior generations, the PFET performance was improved by increasing the Ge content and tweaking the compressive SiN liner.
Figure 14 – Ion vs. Ioff curves for IBM’s high performance 32nm SOI process
IBM achieved impressive AC drive currents (shown above in a regrettably blurry image pulled from an equally blurry PDF) that are equivalent to the performance reported by Intel at IEDM. Fortunately, IBM also started reporting drive currents at the standard leakage level of 100nA/um (as opposed to the rather peculiar reporting at 200nA/um which was used in prior SOI papers). At Vdd of 1.0, IBM achieved AC drive currents of 1550/1220uA/um and DC drive currents of 1500/1180uA/um for NFETs and PFETs.
The paper also called attention to several less obvious implications of a high-k/metal gate stack. One optimization involved reducing the resistance of the gate stack, to improve AC performance – the authors claimed a 10% improvement in FO3 delay as a result. The second was a trade-off between DC drive current and performance. Specifically, the authors found that the best DC drive currents were achieved at the cost of high parasitic capacitance, which decreased the performance (as measured by FO3 delays) by 11%. Thus the process engineers traded away DC drive currents to improve overall performance, and as a side-effect, reducing the capacitance improves active power at fixed frequency.
Figure 15 – 0.149um2 SRAM cell for IBM’s high performance 32nm SOI process
IBM’s SRAM cell size improved by about 5% over prior disclosures at VLSI and IEDM to an impressive 0.149um2, as shown above. Additionally, a 16Mb SRAM array was demonstrated, with low voltage operation at 0.6V. One benefit of the HK/MG stack was lower Vt mismatch, which helps SRAMs operate at lower voltage levels. The contacted gate pitch scaled by 0.7X from the prior generation, down to 130nm.
The interconnect stack is also scaled and has up to 11 layers of copper metallization with ultra low-k dielectrics. Interestingly enough, the paper omits any mention of the previously hyped ‘air-gap’ dielectrics from IBM Research. Air-gap is a bit of a misnomer, since in reality, a vacuum (k=1.0 vs. ~2.4 for ultra low-k) is used to insulate and increase the performance of the interconnect stack. Earlier announcements from IBM claimed air-gap would be integrated into IBM’s 32nm process and in production in 2009. Yet both 32nm IBM papers appear to be using porous SiCOH for the interlayer dielectric.
The most likely explanation for the disappearance of air-gap is twofold: minimal advantages and high risk. For super high frequency chip designs (e.g. 10GHz or more), improving interconnect performance is essential to reducing the FO4 delays per pipeline stage and attaining high frequency. In that context, air-gap would be tremendously valuable. However, since frequency has more or less stagnated (due to power and cooling limitations favoring multi-core), improving interconnect performance is not particularly beneficial – it would only marginally decrease power. While the upside is diminished, the risks of air-gap are still the same – there are substantial mechanical reliability problems. With this change in the risk/reward ratio, IBM’s engineers probably decided to invest their resources in other more advantageous avenues.