IEDM 2010 Process Technology Update

Pages: 1 2 3 4 5 6 7 8

Intel’s Low Power 32nm

Intel’s first paper in session 28 at IEDM 2009 described their 32nm SOC process. As with previous generations, the SOC process is largely derived from the high performance version, but tuned for substantially lower power and with specific features for analog and radio frequency. The SOC process typically lags behind the mainstream high performance variant by roughly 1 year.

The SOC process has three families of transistors – logic, low power logic and I/O devices. The logic transistors all operate between 0.75V to 1V and come in high performance (HP) and standard performance (SP) flavors. The HP logic has similar physical and performance characteristics to Intel’s mainstream process, albeit with a thicker dielectric to reduce leakage. The SP devices are larger to reduce subthreshold leakage further, with a 34nm Lgate, but have similar contacted gate pitch. The reported performance at 1V is 1.17mA/um and 0.87mA/um for 1nA/um Ioff for NMOS and PMOS. The performance is roughly 35% higher than Intel’s 45nm SOC process, and exceeds most comparable process technologies.

The low power logic transistors are used for standby circuits that must always remain on, but are less active overall. The LP transistors focus on minimizing leakage, even at the expense of performance and density. They are designed to operate between 0.75-1.2V, which is significantly higher than the HP or SP options. Higher voltages will increase the power consumption when active, but substantially reduce leakage. The LP transistors are less dense with a 126nm contacted gate pitch and a significantly larger 46nm Lgate. The performance is roughly 60% of the SP option, but with 30X lower leakage. The reported NMOS and PMOS drive currents at 1V are 0.71mA/um and 0.55mA/um for 30pA/um Ioff. The longer gate length and higher voltages reduce subthreshold leakage, but it turns out that the junction leakage was significant enough to require several tweaks to the overall process to control total leakage.

Figure 4 – Low Power Transistor Drive Strength

The high voltage I/O transistors are even larger and are formed with a gate oxide that is 4-7X thicker to deal with the higher voltages in the 1.8-3.3V range. This is a substantial improvement over the 45nm process, which did not have 3.3V transistors.

The SOC process has 7-11 available layers of metal available in 5 sizes: 1X and 1.5X local interconnect, 3X and 4X global routing and then Intel’s signature 8um top layer of metal used for on-die power distribution. In contrast, a CPU optimized process will be tapered with 7 or more different sized interconnects, which human designers can leverage for custom blocks. However, EDA tools are not as capable of using such variety advantageously, so typically SOC processes have fewer options. This is another area where Intel’s 45nm SOC process was atypical, since it used a tapered interconnect stack.

The 32nm SOC process also has its own set of SRAM cells, which were tested in a 291Mbit chip. There is a high density 0.148um2 cell, which is even more compact than Intel’s high performance process. For low voltage and high performance, there is also a 0.171um2 cell (the same size as the ‘dense’ option for high performance).

Figure 5 – Q Factor vs. Frequency for 32nm Inductor

The 32nm process also includes a wide variety of analog and RF devices which are critical for SOCs, but vastly more complex than digital logic that dominates most CPUs. These devices include resistors, capacitors, varactors, inductors as well as analog, power and RF transistors. Session 27.2 at IEDM 2010 analyzed the impact of scaling and high-k/metal gates on analog and RF in the context of Intel’s 32nm SOC process. The overall conclusions were that with the appropriate effort, analog/RF performance has mostly improved with higher drive currents (e.g. improved cut-off frequency), although in some cases it has decreased from 45nm to 32nm (e.g. noise) and there will be significant challenges going forward. One interesting note is that the massive top metal layer (first introduced on Intel’s 45nm process) can be used to create very high performance inductors, as shown in Figure 5.

Pages: « Prev   1 2 3 4 5 6 7 8   Next »

Discuss (16 comments)