IEDM 2010 Process Technology Update

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Common Platform Low Power 32nm

Session 28.2 at IEDM 2009 was a paper from the Common Platform group (IBM, Global Foundries, STMicro, Samsung, Infineon, Toshiba and NEC) describing a 28nm low power process with a high-k/metal gate stack. The process is derived from a previously discussed Common Platform 32nm node. As with all of IBM’s work on 32nm, their process technology uses immersion lithography with double patterning for critical layers and a gate-first approach with a single metal for the gate electrodes. A gate first approach is more readily compatible with existing design rules and has higher density, but substantially lower yields than a gate last transistor stack. Future nodes from IBM will use gate last, due to the needs of IBM’s process technology partners.

The 28nm process is intended to be highly compatible with the existing 32nm process. A 32nm design (or third party IP block) can be easily migrated to the new process, saving on engineering effort and cost, while achieving a reported 10% shrink.

Figure 6 – Low Power Transistor Drive Strength

There are four varieties of logic transistors, and two different I/O transistors. The contacted gate pitch for logic is 114nm, down from 126nm in the 32nm node. The gate oxide thickness is 1.4nm for NMOS and 1.7nm for PMOS devices, with reverse body and source biasing to minimize leakage. With four different logic transistors to choose from, there is a fairly wide spectrum of performance and leakage options for SOC designers. For the highest performance, the super low Vt transistors at 1V and 35nA/um Ioff have reported drive currents of 0.99mA/um and 0.565mA/um for NMOS and PMOS. The high Vt devices operate at 0.54mA/um and 0.305mA/um with 35pA/um leakage. The two intermediate options fill the gap in between, covering three orders of magnitude in terms of leakage. The I/O transistors are substantially larger and target 1.5V and 1.8V operation. The gate length is 3-5X the size of a logic transistor and Tinv is roughly 2X thicker. Overall, the leakage per logic gate in the 28nm node is about 5-10% lower than the 32nm process, largely due to the layout shrink.

The metal interconnects have the same pitch as the 32nm process, and an SRAM array was shown with 7 layers of metal, although more are undoubtedly available. The extremely low-k interconnect dielectric and metallization was improved, which reduced wire capacitance and slightly improved overall interconnect performance.

Two varieties of SRAM can be fabricated, respectively optimized for density and performance. The dense option is targeted for roughly 1V operation and has a 0.12um2 cell. The higher performance 0.152um2 cells are expected to work with ~0.7V, reducing operating power. The high density cell is a substantial 26% improvement over the 32nm process, which reported a 0.157um2 cell, although this assuredly comes at the cost of some performance.

Figure 7 – Q Factor vs. Frequency for 28nm Varactor

As expected, the 28nm SOC process has excellent analog/RF characteristics, and the authors claim to match the performance of existing 28nm process technologies that use a poly-silicon based gate oxide. Varactors (i.e. variable capacitors), which are used for various wireless applications, in particular saw a huge improvement with respect to 45nm. The authors indicate that the high-k gate dielectric enabled substantially thinner gate oxides and improved the tuning ratio by a factor of 20 (versus 45nm). Figure X above shows the varactor Q factor versus frequency, achieving ~38 at 4GHz and ~15 at 10GHz.

In addition to providing a number of device level metrics, the IBM team also provided some insight into the benefits of 28nm for a low power microprocessor. They compared an ARM Cortex-R4F on their 45nm process to the newer 28nm node and achieved a 2.4X area reduction.

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