Process Technology Comparisons
Table 1 continues our tradition of tracking process technologies described at major conferences. It has been updated to include all the nodes described in this article, and some additional gaps have been filled in. It is important to take some of these figures (particularly performance and density numbers) with a grain of salt. Part of the purpose for IEDM and VLSI is to share valuable information and techniques throughout the industry, but there is also a strong element of marketing. For example, not all manufacturers will implement the SRAM cell sizes they describe in papers – due to performance, reliability and yield trade-offs.
Most of the new process technologies disclosed over the last 2 years were focused on SOCs. In fact, the only update for high performance processes is a slight improvement in Intel’s 32nm transistor drive strength, by roughly 5%. That puts Intel’s 32nm performance numbers slightly ahead of IBM. Since the changes are fairly minor, we will not provide an update comparison for high performance nodes, and instead focus on the SOC processes.
Unfortunately, it is incredibly difficult to compare low power optimized nodes. Performance is closely tied to leakage, and there is no widely accepted standard leakage level to use for comparative purposes; in contrast, 100nA/um is a generally accepted level for high performance oriented manufacturing. So any systematic comparison of transistor drive strength is quite complicated and well beyond the scope of this article.
The key density metrics, namely SRAM cell size and contacted gate pitch are much easier to compare across nodes. However, many manufacturers of SOC process technology have avoided reporting contacted gate pitch in various papers. This leaves us with 6 data points from five different manufacturing groups, shown in Figure 10. Nodes marked with a square use a high-k/metal gate stack (except for the 40nm Toshiba/NEC process which uses high-k gate dielectrics only), while those marked with a diamond are for conventional poly-silicon gates. Most of the contacted gate pitch numbers are for low operating power transistors, rather than the low standby power transistors, which tend to be less dense (e.g. Intel’s 32nm low power devices are 126nm vs. 112.5nm).
Figure 11 – Logic and SRAM Density for Low Power Process Technologies
One embarrassing take away is the density of Intel’s 45nm SOC process, which was substantially less dense in terms of SRAM than every other 45nm low power node (0.346um2 vs ~0.25um2). This disparity serves as an example of how important process technology optimization is for semiconductor products. Clearly that has been rectified at the 32nm node, which suggests that Intel’s SOCs may become noticeably more compact going forward.
More intriguing is that the high-k/metal gate process technologies do not seem to have a substantial density advantage over conventional silicon gate oxides. All the 32nm and 28nm process nodes are closely clustered together, showing rough equivalence. Instead, the differences will manifest in terms of transistor performance; it’s quite clear that using HKMG achieves notably higher performance, although perhaps not at all voltage levels.
As a result, the question of when manufacturers will broadly adopt HKMG is an interesting one. Paper 27.2 at IEDM 2010 was solely dedicated to analyzing analog and RF performance scaling in Intel’s 32nm SOC process. The overall conclusion was that HKMG provides comparable or slightly better analog/RF characteristics to a conventional process technology. Thus it seems like the main catch for SOC designers is that most nodes with HKMG are targeted at higher performance than fits their applications. Generally high performance logic is moving to HKMG at 32nm, but it seems like many SOCs will continue to use conventional transistors at 28nm and possibly beyond. In all likelihood, the barrier to adoption of HKMG is probably one of economics – for many SOCs, the additional performance is not justified. So the key drives for HKMG adoption will be decreasing the cost delta, or increasing the performance different to the point where it cannot be ignored. Either way, SOC adoption of high-k/metal gates will be an interesting area to watch in the coming years.