IEDM 2010 Process Technology Update

Pages: 1 2 3 4 5 6 7 8


Exploring research and development in process technology and device physics is the purpose of IEDM, and the process technology track at VLSI Symposium. The trend at IEDM 2008 was the adoption of high-k/metal gate transistors by manufacturers that focus on high performance logic. This was the innovation needed to maintain good performance while scaling density according to Moore’s Law.

The trend at IEDM and VLSI in 2009 and 2010 is that SOC manufacturing is just starting to explore high-k/metal gates. The motivation is the same – achieving good performance at ever smaller geometries, but the need is much less acute. HKMG was first deployed by Intel in their 45nm high performance node and then a year later in the SOC variant. It took three years for high performance logic manufacturers to catch up with Intel, at the 32nm node and an extra year or two further for low power process technology to begin a similar adoption curve. The embrace is cautious and far from universal – demonstrating the diversity of needs in the SOC world. Fundamentally, the economics will dictate which market segments turn to HKMG – high performance logic places the highest economic value on transistor performance, and thus was first to adopt. For many other applications, performance is not enough of a consideration to merit changes at the moment. However, this calculus may change over time as the performance advantage of HKMG increases relative to conventional transistors, or the cost premium falls.

IEDM 2010 was unique in that the focus was almost exclusively on research, and not a single leading manufacturer presented details on their upcoming 22nm process nodes. The most likely explanation is reluctance to disclose details that could give valuable insights to competitors. The sheer breadth of research papers focusing on extending CMOS to 15nm and beyond make it clear that 22nm should have no fundamental barriers. Moreover, Intel has already taped out a 22nm microprocessor, suggesting that 22nm is healthy.

The real question is what changes will be required to maintain and improve performance at 22nm. Starting at 90nm, each generation of process technology has required more innovations to improve performance. Strained silicon, raised source/drains, high-k/metal gates have all been deployed to keep semiconductor scaling on track. But what is next? A number of alternative transistor architectures have been discussed, including multi-gate transistors (e.g. FinFETs), fully depleted SOI substrates or III-V materials for the transistor channel, although these seem to be somewhat further out in the future.

As the effort required to scale continues to grow, another trend will continue to accelerate – the shift of companies away from internal manufacturing towards a fabless or hybrid model. Reports indicate that Toshiba will cease development of advanced process nodes and instead partner with Samsung for logic production. Fujitsu and TI both went into production at the 45nm node and then stopped; Toshiba was only able to continue an additional generation. One observation is that the most substantial changes to manufacturing are most likely to narrow the field and further separate out the first class IDMs and foundries from the followers. The challenge of incrementally improving a planar transistor is far less than trying to move to FinFETs or other fundamentally different approaches.

For now, it seems like the three leaders in logic manufacturing, IBM/Global Foundries, Intel and TSMC, are all set to continue pursuing Moore’s Law. Intel and TSMC have the volumes and revenues to justify further investment, while IBM and Global Foundries have the financial resources to continue development and potentially grow their volumes to match. While Samsung has indicated they will aggressively seek foundry business, their R&D is closely tied to IBM’s and it is not obvious that their success in DRAM will translate into many logic customers.

A more subtle question is the pacing. Historically speaking, Intel was 12-15 months ahead of AMD and IBM in manufacturing. At 32nm, this lead has increased to 18 months with respect to Global Foundries and AMD. It is entirely unclear whether this is a long term trend, or merely an artifact of IBM’s ill-fated choice of a gate-first process technology. On one hand, Global Foundries’ benchmark is TSMC – which is the leader of the foundry industry and their chief competitor. But IBM’s server CPUs and systems clearly compete with Intel’s. The 22nm node will confirm whether TSMC and IBM/Global Foundries can keep apace with Intel, but those disclosures are unlikely to happen until later this year at VLSI or IEDM 2011.

Pages: « Prev  1 2 3 4 5 6 7 8  

Discuss (16 comments)