Intel’s 22FFL Process Improves Power, Cost, and Analog

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To date, Intel has introduced two generations of FinFET-based process technologies, each comprising several different variants (e.g., 14nm, 14nm SoC, 14+, and 14++). All of these process technologies are primarily focused on high-performance digital logic, befitting a company that specializes in manufacturing processors. Intel’s analog designers are responsible for creating circuits such as PLLs (for clocking) and PCIe (for I/O) that are critical for modern SoCs on a process that isn’t optimized for analog. In some cases, Intel’s design team produces new digital equivalents (e.g., digital temperature sensors and digital PLLs), while in other cases, they simply do their best within the limitations. For ASIC-like design flows, Intel’s process is fairly complex and the extra performance is not necessarily valuable.

To meet the needs of products with more automated design and analog and RF circuitry, Intel’s logic technology development (LTD) team in Hillsboro, Oregon went to the drawing board and came up with 22FFL (FinFET Low-power), a variant of their existing 22nm process technology that is aimed at low-cost, extremely low-power, and analog/RF applications. The 22FFL process relaxes the ground rules to reduce the need for double patterning, thereby cutting costs. At the same time, Intel’s engineers essentially backported the second and third generation FinFETs from the 10nm and 14nm process to 22FFL, improving performance and power efficiency with superior fin geometry and workfunction metals. The LTD team created a large library of transistors that includes 3 high-performance logic, 3 low-power logic, an ultra-low leakage logic, 3 analog, and 3 high-voltage devices and a variety of passive components such as inductors and resistors.

Relaxed Metal Stack Cuts Costs

As Table 1 illustrates, the 22nm SoC and 14nm SoC interconnects are optimized for high-performance with a hierarchy of tapered metal layers that offer different pitches. While not shown in the chart, many of these layers also vary the wire aspect ratios and insulating dielectric materials to separately optimize wire resistance or capacitance.

At the 22nm node, Intel adopted double-patterning for a single 90nm pitch metal to support 2D routing and complex layout shapes. In contrast, the 80nm minimum pitch layers could only route in a single dimension due to the limitations of single-exposure immersion lithography. At the 14nm node, the metal interconnects scaled significantly, but required more lithography steps, increasing wafer cost. All sub-80nm pitch metal layers were formed using self-aligned double patterning (SADP) and are uni-directional. The 80nm pitch layers are uni-directional with single patterning, while the looser pitch layers are more flexible.

Intel 22FFL Metal Stack

Table 1 – Metal layers for Intel’s 22nm SoC, 14nm SoC, and 22FFL process technologies.
* indicates uni-directional pitches.
‡ indicates multi-patterning.

Intel’s 22FFL metal stack is similar to a foundry SoC process and includes three novel layers. The metal layer pitches are all integer multiples and generally optimized for low-cost. Intel’s team chose a minimum pitch of 90nm for the lowest 6 layers. Unlike previous Intel process technologies, this metal 1X layer supports complex routing using only single-patterning lithography, eliminating a second exposure compared to the 22nm SoC process. Two thick metal upper layers are available for routing power and ground, and they are also used to form inductors and metal-insulator-metal capacitors. The 1080nm pitch metal layer is re-used from existing process flows, but the 4000nm pitch top metal layer is entirely new. In addition, the process flow supports optional 2X, 4X, and 8X pitch metal layers; the 720nm 8X pitch is also a new layer defined specifically for the 22FFL node.

Compared to 22nm SoC, the 22FFL metal interconnects are much easier for modern EDA tools. Supporting complex shapes in a large number of similar metal layers avoids restrictive design rules and splitting shapes across multiple layers, which enables automated tools to generate denser layouts. This is particularly important for foundry customers, which are not familiar with Intel’s highly restrictive design rules, and for ASIC-like designs (e.g., modems) where clock frequency does not directly translate into value. In contrast, the tapered interconnect hierarchy for the 22nm and 14nm nodes can achieve higher performance, but only by carefully taking advantage of the unique characteristics of each layer, which is difficult for automated tools.  

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