New Transistors Boost Performance
The transistors for Intel’s 22FFL bear little resemblance to the older 22nm process, and instead are derived from the more advanced 14nm and 10nm process technologies. As Table 2 illustrates, the only physical characteristic that the 22FFL transistors share with the 22nm SoC process is the relatively loose 108nm gate pitch, which enables a longer gate length. The actual 22FFL fin pitch, height, and width are comparable to the 14nm transistors, and the geometric similarities do not end there.
As Figure 1 illustrates, the 22nm transistors are trapezoidal, which is not ideal for performance or power efficiency, but is still leagues better than planar transistors. At the 14nm node, Intel moved to a taller and more vertical fin and adopted a technique known as sub-fin doping; these changes improve performance, variability, and leakage. The 22FFL transistors share the same vertical geometry with the 14nm transistors and appear to use sub-fin doping; both nodes also target a 0.7V operating point compared to 0.75V for 22nm SoC.
The 22nm and 14nm SoC processes create high VT transistors (e.g., for the low-power, low-leakage devices) by implant doping. Unfortunately, the statistical nature of doping often increases variability of a transistor type (or σVT). In a typical design, the slowest transistors (i.e., the highest VT) tend to determine the operating voltage needed to hit a given frequency. As a result, a larger σVT for high VT devices will directly increase the voltage and therefore the power consumption of a chip.
The 22FFL transistors are tuned in a novel fashion that improves power-efficiency by using different workfunction metals (Intel’s 10nm process and IBM’s 14nm FinFET process also use a similar technique). Intel’s 22FFL process flow offers several different gate lengths and two workfunction metals to set threshold voltages. The high-performance transistors comprise three different gate lengths: ULVT (32nm), LVT (36nm), and LPLVT (44nm). The low-leakage transistors (HP, nominal, and LP) use the same gate lengths, but with a different workfunction metal to increase the threshold voltage. These high VT transistors actually have less variability than the low VT devices (whereas implant doped high VT transistors tend to have worse variability) and enable lower operating voltages. Intel reported that the highest VT single-fin NFETs/PFETs had σVT of 13mV/14mV. All six of these digital transistors share are footprint compatible, with a 108nm contacted gate pitch. As Figure 2 illustrates, the 22FFL is much faster than the 22nm SoC process, with 57% and 87% higher drive currents for NMOS and PMOS devices.
Intel’s design team also created a new ultra-low-power logic (or LL) transistor that minimizes leakage for always-on logic. To increase VT even further, the new LL transistor has an even longer gate length than the low-power transistors and is much larger, requiring a contacted gate pitch of 144nm. It also uses a very thick gate oxide, similar to high-voltage I/O transistors, which reduces leakage. The new LL transistors have a total leakage below 0.5pA/µm and 0.7pA/µm for NMOS and PMOS. In comparison, the lowest leakage ULP transistors in the 22nm SoC process have 15pA/µm sub-threshold leakage and additional source-drain and junction leakages.
Intel offers two different circuit libraries on the 22FFL process. The first was disclosed by Mark Bohr and is 630nm, or 14 fin pitches in height, and optimized for performance. The second library is tuned for density and uses 540nm high cells.