New Memory, Analog, and RF Building Blocks
SRAMs typically use low-leakage, high VT transistors, so Intel designed a new set of three SRAM bit-cells for the 22FFL process. A high-density 0.087µm2 cell and a high-current 0.107µm2 cell use the regular low-power transistors. The former use single-fin devices while the latter uses some multi-fin devices and offers about twice the read current. The thick-oxide LL transistors are used in an extremely low-leakage cell that has a median leakage under 1pA, which is 28X less than the regular high-current cell, but has about a fifth the read current of the HCC cell.
As Figure 3 illustrates, the new bit-cells enable <0.5V VMIN operation for modest-sized arrays. The HCC data is for a 32Mbit array, while the HDC and HCC-LL data are from smaller 16Mbit arrays. The HDC cells are used in conjunction with write-assist circuitry. The low-leakage array operates with a 95th percentile VMIN of 0.71V.
In addition to the logic transistors, 22FFL also includes 3 analog and 3 I/O devices. The long-channel analog transistors are larger than the digital devices – with 144nm, 216nm, and 270nm contacted gate pitches, corresponding to 74nm, 120nm, and 160nm gate lengths. The new analog transistors increase GM*ROUT (an analog figure-of-merit) by 3.3-4X compared to the 22nm SoC process. Using these analog transistors, Intel’s design teams built a 3.2GHz PLL that operates at 0.85V and draws 0.77mW. Intel’s team also presented several RF metrics for the 22FFL process. The unity current gain (FT) frequency was reported as 230GHz/238GHz and the unity power gain (FMAX) as 284GHz/242GHz for NMOS/PMOS respectively. As Figure 4 shows, the team is still optimizing and expects to exceed 300GHz for FT.
Like the analog transistors, I/O transistors are also larger footprint, with 216nm and 270nm contacted gate pitches. However, they use a thick gate oxide to support stable 1.2V, 1.5V, and 1.8V operation for off-chip interfaces. Compared to the 22nm SoC process, the I/O transistors are 33%/35% higher current for NMOS and PMOS. Although no 3.3V devices were described, the 22FFL I/O transistors are fairly close in performance to the I/O devices in the 14nm SoC process.
For passives, the 22FFL process includes 3 different inductors formed in the thick metal layers that are 150µm, 175µm, and 225µm wide. All the inductors can hit quality factors of 28-31 and they respectively offer about 0.17nH, 0.22-0.26nH, and 0.33-0.45nH. Metal-insulator-metal capacitors are also supported in the thick upper metal layers, along with capacitors in lower layers.