Intel’s 22nm Tri-Gate Transistors

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In practical terms, Intel’s 22nm tri-gate transistors are a significant advantage for the company. Moving to a smaller node typically improves performance by around 10-15%. For operating voltages near 0.85V, Intel is essentially improving performance by an entire extra process generation, and more at 0.7V. Even taking Intel’s estimates conservatively, that suggests a performance/watt advantage of 10-20% for power optimized chips versus a planar 22nm process.

The other leaders in semiconductor manufacturing all indicated they will continue to scale conventional transistors for the next generation. TSMC and Global Foundries both announced FinFETs for the 14nm node. The foundries must move slower because FinFETs require changes in circuit design (especially analog), tools and IP throughout the whole ecosystem. External partners may be unprepared for the transition, but are necessary for the foundries. Intel (or IBM) can shift their design infrastructure much faster, since it is almost entirely internal and they do not rely on an extensive partner network.

As it stands today, Intel is roughly 18 months ahead of IBM, Global Foundries, TSMC and Samsung on their process technology. Intel began shipping 32nm parts in late 2009, while AMD started shipping 32nm parts from Global Foundries in April, 2011. Xilinx claims to be sampling 28nm FPGAs fabbed at TSMC, but volume shipments will happen later, and more complex designs will also take longer to ramp. The most likely scenario for 22nm is that Intel begins shipping at the end of 2011 or early 2012 and the foundries follow with 20nm products in 2013. Intel will have a ~18 month window with a twofold manufacturing edge over their competitors. First, they will gain a full process node in terms of density and power/performance and second, the additional benefits of FinFET transistors. After these 18 months, the gap will narrow, but Intel will still have FinFETs to themselves for another 2 years. The lingering questions are how Intel will translate a manufacturing advantage into products, and how yields will shape up for such a novel process.

The impact of tri-gate transistors is most pronounced for power constrained products, such as those targeting tablets or phones – coincidentally, where Intel also needs the most help. The logical approach is to primarily use the benefits of 22nm to reduce operating voltage and drive down power consumption by 20-30% versus 32nm/28nm and ~10-20% compared to 22nm/20nm. The market for smartphone SOCs is held by a number of entrenched competitors that all license their processors from ARM – Qualcomm, Texas Instruments, Samsung, Apple, ST-Ericsson and others. Going up against this ecosystem is very challenging, and Intel will need a concrete advantage to make significant inroads.

Historically, Intel’s SOC manufacturing lags 12 months behind their high performance process. Their first fully integrated SOC (32nm Medfield) has yet to ship in products, and is expected in the latter half of this year. If Intel aggressively moves forward at 22nm, their SOCs might follow high performance manufacturing by 6 months. That would create a 12 month window of opportunity, where Intel has a 2X density and 20-30% power efficiency advantage over their competitors from FinFETs and a full node shrink. Naturally, their software and hardware ecosystem partners would also have to keep pace. Even this is no guarantee for success, but it certainly creates highly favorable conditions for breaking into a new market.

Intel is planning to build or upgrade five 22nm fabs in Oregon, Arizon and Israel throughout 2011 and 2012. Presently, they have four 32nm fabs in production. The increase in capacity is clearly intended for expansion into the embedded and mobile markets. While smartphones may be an uncertain proposition, Intel is doing well in other embedded areas and looking to continue that growth. This creates risk, should their plans for the handset market go awry, but in the case of owning a fab – there is no opportunity without risk.

Speaking of risk, there are a host of challenges with FinFETs. These problems include variation in the dimensions and smoothness of the fin, implementing strain, capacitance between the gate and source/drain, and resistance between the gate and source/drain. Given the massive changes in the process technology, there is a risk that Intel may experience some yield issues. While they would not go forward with tri-gates unless they were confident that they could reach mature yields, the ramp in production and learning curve may be slower than for conventional planar CMOS.

Looking forward, Intel will describe their 22nm process technology in detail at IEDM, later this year. Hopefully the presentation shall discuss many of the complexities of FinFETs and share insights on the challenges they encountered and the solutions that are needed to achieve good results. Intel’s FinFET process is a preview of how the rest of the industry will implement FinFETs at the 14nm half-node. Shortly after IEDM, Intel will release the 22nm Ivy Bridge, and consumers will get to see for themselves what FinFETs can achieve.

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