Regular Interconnects Simplify Design and Manufacturing
In many respects, the biggest changes to Intel 4 are beyond the transistor and instead lie in the interconnect stack. Intel’s LTD team rearchitected the overall stack to be much more regular compared to the 10nm family (which includes Intel 7), changed the materials used, and judiciously introduced EUV.
Table 2 – Intel 7 and 4 interconnect comparison
As Table 2 illustrates, the interconnect stack scaled – but in a complicated fashion that defies simple comparisons. The stack comprises a total of 18 metal layers including 16 regular metal layers and two thick upper metal layers. Generally speaking, the tighter layers of the Intel 4 interconnect architecture are highly regular. In the vertical direction, the fins and M0 are 30nm pitch and in the horizontal direction the contacted gate and M1 are all 50nm pitch. Moving up the stack, the M2 and M4 layers are a simple 1.5X scaled pitch relative to the tightest vertical pitches, while the M3 has the same pitch as the horizontal layers. These regular dimensions at the lowest layers of the interconnect stack simplify automated design and layout as well as design for manufacturing.
The regular pitches also work well for the new gridded interconnect system of Intel 4, which simplifies the design space and reduces process variability, improving performance and yield. In prior nodes, the design rules specified a minimum spacing between vias as well as a minimum endcap for metal lines connecting to vias – these rules are necessary to handle potential edge placement errors (EPE) that arise during fabrication while ensuring good yield. In the gridded interconnect system of Intel 4, vias are placed on a regular grid – rather than just being constrained by a minimum spacing. Similarly, the length of metal lines is regularized.
Figure 5. Intel 4 gridded interconnect
Figure 5 illustrates one of the benefits of the gridded interconnect – the fixed length endcaps on the blue metal layer no longer overlap the orthogonal white metal layer (the orange circles), which reduces capacitive coupling and will improve interconnect performance. The other benefit is that more regular layouts allow the lithography team to aggressively optimize the mask for the source illumination, improving printability and yield. The downside is that this regularity may reduce the achievable density for standard cell designs. However, it is likely that the performance and yield benefits are an overall win when considering the cost of a fully yielded design.
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