Semiconductors Live in a Material World
From a materials standpoint, Intel 4 is a significant departure from the prior generation and a return to traditional materials used in new ways. Intel has significantly retreated on the use of cobalt (Co) and opted to employ and enhance more traditional materials such as copper (Cu) and tungsten (W). On the initial 10nm process, Intel employed cobalt in the contacts as well as the metallization and vias for the two tightest pitch metal layers (40nm M0 and 36nm M1).
Switching from copper to cobalt at 10nm was primarily motivated by scaling concerns. At small dimensions, the volume of copper in a wire decreases significantly because it requires complex barriers and liners compatible with the dielectrics and metal chemistry that are difficult to scale. The lower volume of copper increases line and especially via resistance, and reduces reliability due to electromigration. Cobalt offers worse line resistance than copper as a material, but uses much thinner and simpler barriers and liners and has better electromigration properties.
At the 10nm node, Intel reported that cobalt reduced the contact line resistance by 60% compared to traditional tungsten contacts. Forming cobalt vias with a titanium liner reduced resistance by about 0.6X compared to copper with traditional tantalum nitride (TaN) liners. The actual line resistance for wires got worse due to the higher intrinsic resistance of cobalt, but electromigration (EM) lifetimes improved by 1,000X and 50,000X for cobalt capping and pure cobalt respectively. Unfortunately, cobalt is also a fairly difficult material to work with and is suspected to be one of the key yield challenges that Intel encountered on the 10nm family.
At smaller geometries, the contact layer is increasingly challenging due to alignment requirements, resistance, and potential capacitance between the contact and gate. A typical contact hole will be 20nm or less in diameter. Intel explicitly indicated that the metal has reverted from cobalt back to pure tungsten and that a single damascene process is used to form the contacts separate from the M0 layers. It is extremely likely that the contacts are printed using EUV. The switch from cobalt back to tungsten also implies that the contacts use a different process flow that increases the volume of tungsten which likely improves the contact resistance compared to the cobalt-based Intel 7.
Figure 6. Intel 4 and 7 metal layer metallurgy
As with contacts, the most challenging aspect of metal interconnects are the vias and the barriers and liners that surround the metal wiring. Typical copper interconnects are doped to reduce electromigration (EM) problems. For Intel 4, the tight pitch M0-M4 layers all switched to a new copper-based metallurgy as shown in Figure 6, replacing a combination of cobalt and copper alloy metallization. The enhanced copper metal layers eliminate the high-resistance and high-volume TaN liner/barrier, and instead use a combination of tantalum and cobalt. The cobalt lining should solve the EM challenges, which enables using pure copper instead of a doped alloy. The copper is reflowed after deposition to improve the fill and reduce or eliminate voids and then finally capped with cobalt.
Intel did not discuss via resistance, which is largely a function of the resistance of the barriers and liners. Here the thinner barriers and liners of the enhanced copper layers should improve via performance compared to the vias for the copper alloy layers in Intel 7 and potentially match or improve on the vias for the cobalt layers.
Figure 7. Intel 4 and 7 interconnect performance and reliability
Figure 7 shows a detailed comparison of the enhanced copper layers against both the cobalt and copper alloy metallurgy used in comparable layers in Intel 7. The Intel 4 enhanced copper layers have slightly worse EM lifetime than pure cobalt, essentially resolving reliability concerns. The line resistance is ~18% better than copper alloy or a whopping ~38% better than pure cobalt, a major contribution to the improved interconnect performance in Intel 4. The overall result is that for the finest pitch interconnects, simple geometric scaling would actually worsen the metal RC by about 50%, but due to the material engineering, RC decreased slightly for Intel 4.
Pages: « Prev 1 2 3 4 5 6 7 Next »
Discuss (43 comments)